Tharas Systems Unveils Industry's First Family of Verification Appliances; New Hammer S-Class and M-Class Deliver Market Leading Productivity Boost for SoC and Embedded System Verification.SANTA CLARA Santa Clara, city, Cuba Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. , Calif. -- Tharas Systems, Inc., a leading provider of high-performance, hardware-assisted verification solutions, today significantly altered the landscape of the electronic design automation market, as it unveiled the first two new products in a series of next-generation Hammer(R) verification appliances. The Hammer S-Class and M-Class are based on a new multi-core, custom processor chip designed by Tharas Systems, enabling verification run-time speeds of hundreds of kilohertz One thousand cycles per second. See Hertz. . These new verification appliances also deliver the industry's first 'virtual emulation' capability, Hammer Virtual Connect(TM), a software-model based approach that targets key vertical application segments and offers a powerful solution for embedded software Instructions that permanently reside in a ROM or flash memory chip. Embedded software may be immediately available to the CPU or, for faster execution, may be transferred to RAM first and then executed. verification and concurrent hardware-software validation. "Our customers continue to experience ever-increasing pressures for first-pass silicon success, requiring extensive chip-level and system-level functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, within shortened project schedules. In response to these requirements, Tharas has dedicated significant resources over the past several years toward development of these new Hammer products," stated Rahm Shastry, president and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of Tharas. "The appliance-like characteristics of the S-Class and M-Class, combined with the newest generation of our custom-processor architecture, deliver break-through price/performance and ease-of-use." The modular series maintains Tharas' leadership position with plug-and-play, event-accurate Verilog and VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. simulation acceleration, and extends the products' utility into embedded system verification. The rack mountable, single user Hammer S-Class addresses the needs of logic and system designers for up to 16 million ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. gates, while the multi-user M-Class addresses the needs of design teams developing systems up to a complexity of 64 million ASIC gates. Further details on the Hammer Virtual Connect product can be found in the accompanying press release from Tharas, dated June 6, 2005. Significantly Faster Acceleration The new Hammer family strengthens Tharas' leadership in plug-and-play simulation acceleration to introduce two additional modes of operation; high performance transaction-based and test bench acceleration, architected to deliver up to 1000X performance improvement over the fastest software simulator. The high-performance transaction-based acceleration supports the Accellera Standard Co-Emulation Modeling Interface (SCE-MI) API standard, de-coupling the software simulator from the high-performance Hammer families to accomplish an optimal mix of bandwidth and communication latency. Fastest Turn-Around-Time By virtue of the efficient custom-processor architecture, the new Hammer family is able to achieve ultra-fast compile times of up to 90 million RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; equivalent gates per hour using a single compute resource. Incremental changes can be made to the test bench or the design blocks without having to re-compile an entire environment. Unlike other hardware-assisted tools based on commercially available FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. technology, the Hammer compiler directly maps HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. code to the instruction set of the Tharas custom processor, thereby eliminating the need to map RTL to gate-level primitives. Breakthrough Custom Processor Architecture for Faster Speed Powered by an industry proven 130-nanometer silicon process, the new multi-core, custom-processor integrates high-speed 1T-SRAM(R) with 32 processor cores, trace logic and ultra-wide Arithmetic Logic Unit See ALU. (ALU (Arithmetic Logic Unit) The high-speed CPU circuit that does calculating and comparing. Numbers are transferred from memory into the ALU for calculation, and the results are sent back into memory. Alphanumeric data are sent from memory into the ALU for comparing. ). The proven and patented architecture enables direct low-latency communication between every processor with an I/O (Input/Output) The transfer of data between the CPU and a peripheral device. Every transfer is an output from one device and an input to another. See PC input/output. I/O - Input/Output clock rate of 200MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. . The new custom processor also triples the instruction set so that complex operations can be done in a single clock cycle. It uses state-of-the-art flip chip technology to enable high-speed switching. The benefit of the new custom processor chip is the radical boost in the run-time performance. Using the new Hammer families, design and verification teams can realize simulation speeds of hundreds of kilohertz. The faster run-time speeds enable designers to execute significantly more numerous and longer tests to finish RTL and system-level validation with a higher degree of first-pass confidence. Product Unveiling at DAC See D/A converter and discretionary access control. DAC - Digital to Analog Converter 2005 The new generation of Hammer appliances will be demonstrated at the Design Automation Conference, DAC, in Anaheim, California, June 13-16, 2005, at the Tharas exhibit booth, #1001. For more information about the unveiling event taking place on Monday June 13, at 10:00 a.m., visit http://www.tharas.com/dac05. Pricing and Availability The Hammer S-Class and M-Class products are available either through purchase or time-based rental. For users wishing to rent these systems, the Tharas Flexible On-demand Rental Collaborative Environment (T-FORCE), is available for a minimum of a six month rental period. In the US, monthly rental pricing for Hammer SX starts at $14,000 for 4 million gate capacity and the Hammer MX monthly rental fee starts at $52,000 for the 32 million gate configuration. The Hammer Virtual Connect solution is available as an add-on option for both systems. Tharas will begin shipping the new Hammer S-Class and M-Class systems worldwide in Q3 2005 and supports the Sun Solaris and Linux platforms. Existing Hammer 100 customers will have an option to upgrade to the new product families. About Tharas Systems Tharas Systems develops and markets design verification appliances that lead to a significant shortening of the overall verification cycle of complex integrated circuits and electronic/embedded systems. The pay off is a demonstrable reduction in time-to-market due to enhanced verification productivity. The newly introduced Hammer(R) S-Class and M-Class product families incorporate a patented, multi-core, custom-processor hardware assisted engine developed by Tharas for use in Verilog- and VHDL-based SoC and embedded system verification, delivering the fastest compile and run time speed-up, combined with ease-of-use and extensive debugging capabilities. Customer installations span the communications, computers, graphics and networking industries. Founded in 1998, Tharas is privately held with corporate headquarters located in Santa Clara, California Santa Clara, California (IPA: /ˌsæntəˈklærə/) , founded in 1777 and incorporated in 1852, is a city in Santa Clara County, in the U.S. state of California. , and regional sales and support offices in North America and Japan. Tharas products are distributed through channel partners in Europe, India and Korea. For more information, see the company website, http://www.tharas.com. Hammer(R) and Virtual Connect are trademarks of Tharas Systems Inc. Tharas acknowledge trademarks or registered trademarks of other organizations for their respective products and services. |
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