Tharas Systems Sets New Price/Performance Yardstick for Hardware-Assisted Verification Acceleration.Business Editors/High-Tech Writers SANTA CLARA Santa Clara, city, Cuba Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. , Calif.--(BUSINESS WIRE)--June 11, 2001 Hardware Acceleration In computing, hardware acceleration is the use of hardware to perform some function faster than is possible in software running on the normal (general purpose) CPU. Examples of hardware acceleration include blitting acceleration functionality in graphics processing units (GPUs) and Supplier Announces Immediate Availability of 2 and 4 Million RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; Gate-Equivalent Capacity Accelerators Electronic Design Automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) supplier Tharas Systems Inc., today announced immediate availability of 2 Million and 4 Million RTL gate-equivalent Hammer(TM) Hardware Accelerators, in addition to its flagship 8 Million gate-equivalent configuration. "The industry is looking for Looking for In the context of general equities, this describing a buy interest in which a dealer is asked to offer stock, often involving a capital commitment. Antithesis of in touch with. acceleration to speed up verification cycles. We believe the addition of these new configurations at compelling price/performance points will advance widespread usage of RTL hardware acceleration," said Prabhu Goel, Chairman & CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of Tharas Systems. Hammer(TM) 2M is priced at US$115,000 for a 2 Million RTL gate-equivalent capacity, while Hammer(TM) 4M which is capable of accelerating 4 Million RTL gate-equivalent designs is priced at US$185,000. The new configurations offer the same simulation speeds as the flagship Hammer(TM) 8M, the 8 Million RTL gate-equivalent high-end systems. "Multi-million gate designs can easily fit into our low-end configurations due to our massively parallel See MPP. , HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. instruction-based architecture and our capacity estimates are conservative. On the other hand, competing FPGA-based systems have severe capacity limitations due to issues with partitioning and utilization among FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. devices. For instance, a 4 million RTL gate-equivalent, FPGA-based competing system lists at $400K and is often unable to accommodate even a 2 million gate-equivalent design. The attractively priced Hammer(TM) 2M and Hammer(TM) 4M will break the barrier to adoption for most design teams. It is also important to note that our low-end offerings do not compromise on performance; they run just as fast as the flagship 8 Million gate box" notes Rahm Shastry, Senior Vice President of Marketing & Sales at Tharas Systems. About Hammer(TM) Hammer(TM) is an affordable and easy-to-use patented ASIC-based hardware accelerator for Verilog simulations with ease of use and debugging capability comparable to that of software simulators. It fits seamlessly into existing design environments, offering high performance and capacity - while compile times are comparable to software simulators at a rate of 1 Million Gate-equivalent compiles in 6 minutes, the run times are anywhere from 10 to 50 times faster than software simulators. Hammer(TM) can reduce the time to achieve a functionally correct chip or system by 50% of a typical 6-month verification schedule for a million-gate design. Offering hardware near emulator performance, Hammer(TM) is the only hardware accelerator solution that easily fits in either iterative, design-debug phase or regression phase because if its blazingly fast set up times. It supports design sizes of up to 8 million gates of equivalent RTL code, and can be combined with multiple memory models up to one Gigabyte in hardware. Hammer(TM) is packaged in a standard off the shelf CompactPCI chassis and power supply. The chassis uses a proprietary backplane that delivers more than 10Gbps bandwidth. Hammer(TM) is designed to work transparently within an existing RTL verification environment. As a result, designers can continue to use familiar verification software, including the most popular Verilog HDL-based simulators from Synopsys, Inc. (Nasdaq:SNPS SNPS Space Nuclear Power System ) and Cadence Design Systems (company) Cadence Design Systems - A company that sells electronic design automation software and services. http://cadence.com/. See also Verilog. , Inc. (NYSE NYSE See: New York Stock Exchange :CDN (Content Delivery Network) A system of distributed content on a large intranet or the public Internet in which copies of content are replicated and cached throughout the network. ), debugging and testbench-generation software and C language models. Pricing and Availability Hammer(TM) 2M is priced at US$115,000 for a 2 Million RTL gate-equivalent capacity and 250 Mbytes of memory. Hammer(TM) 4M is priced at US$185,000, which is capable of accelerating 4 Million RTL gate-equivalent capacity and 500 Mbytes of memory. Hammer(TM) 8M which can accelerate has 8 Million RTL gate-equivalent capacity with 1Gbyte of memory is priced at US$280,000. All Hammer(TM) configurations are available immediately. Hammer(TM) is marketed and sold through an international direct sales channel, with extensive customer support. For more specific product information, email info@tharas.com or call 408/855-3200 About Tharas Systems Tharas Systems develops and markets high performance verification systems to designers of complex integrated circuits Integrated circuits Miniature electronic circuits produced within and upon a single semiconductor crystal, usually silicon. Integrated circuits range in complexity from simple logic circuits and amplifiers, about 1/20 in. (1. and electronic systems. The Tharas solution leads to significant shortening of the verification cycle; the pay off is material reduction in time-to-market. Tharas System patented hardware accelerator Hammer(TM) is the only solution that speeds up both the simulation of the design as well as execution of the test bench. Simulation acceleration applies to behavioral, RTL, and gate level representations. Increasing verification complexity is one of the main challenges of designing complex integrated circuits and systems today. Founded in 1998, Tharas is privately held and funded by venture capital and private investors from throughout the electronics industry. Corporate headquarters is located at 3016 Coronado Drive, Santa Clara, Calif. 95054. Visit Tharas Systems at http://www.tharas.com. Hammer(TM) is a trademark of Tharas Systems Inc. Tharas acknowledges trademarks or registered trademarks of other organizations for their respective products and services. Note to Editors: A photo of Hammer(TM) is available upon request |
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