Tharas Systems' Hammer Hardware Accelerator Adopted by NVIDIA to Verify Next Generation 3D Graphics Chips.Business Editors/High-Tech Writers SANTA CLARA Santa Clara, city, Cuba Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba. , Calif.--(BUSINESS WIRE)--Oct. 21, 2003 Tharas Systems, Inc., a provider of high-performance, hardware-assisted design verification solutions, announced today that NVIDIA Corporation, the worldwide leader in visual processing solutions, has selected Tharas Systems' Hammer hardware accelerator to assist in verification of its next-generation 3D graphics processor. "Hammer's plug-n-play acceleration nicely supplements our existing verification flow," says Narendra Konda, Hardware Emulation Manager at NVIDIA Corporation. "Hammer has reduced our early-stage verification cycles, wherein RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; is constantly changing with its fast compile, run-time and productive debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. environment." Full-chip verification with Hammer was an order of magnitude A change in quantity or volume as measured by the decimal point. For example, from tens to hundreds is one order of magnitude. Tens to thousands is two orders of magnitude; tens to millions is three orders of magnitude, etc. faster than software simulation while not compromising a productive debug environment. "We are honored that NVIDIA chose Hammer over competitive solutions. It is a well known fact that NVIDIA relentlessly pushes the technology envelope and this is a clear recognition of Hammer's unique value proposition," notes Rahm Shastry, President and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of Tharas Systems. "Hammer's accelerated verification approach is unparalleled for its transparency, speed and debug efficiency at one-third the cost of competitive solutions." About Hammer Tharas Systems' Hammer provides Verilog, VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. and mixed language accelerated simulations with the fastest compile and run times, while at the same time offering ease of use and debug capabilities comparable to that of software simulators. Compile times are as fast as 50 Million RTL Gates per hour on a single workstation vs. several hours per Million RTL gate-equivalent for competing FPGA-based systems. Run times can be as fast as 10,000 times the software simulators. Hammer's innovative hardware architecture is based on the state-of-the-art custom processor technology that outflanks Rent's rule and a proprietary backplane that delivers more than 10 Gigabits per second bandwidth, thereby minimizing run time degradation during debug. In addition, Hammer offers 100% source-level visibility without having to reconstruct signals - a significant improvement over other hardware-assisted verification solutions. Hammer works with existing RTL and gate-level verification environments. As a result, designers can plug-n-play their existing verification software, including the most popular Verilog HDL-based simulators from Synopsys, Inc. (NASDAQ NASDAQ in full National Association of Securities Dealers Automated Quotations U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on : SNPS SNPS Space Nuclear Power System ), Cadence Design Systems (company) Cadence Design Systems - A company that sells electronic design automation software and services. http://cadence.com/. See also Verilog. , Inc. (NYSE NYSE See: New York Stock Exchange : CDN (Content Delivery Network) A system of distributed content on a large intranet or the public Internet in which copies of content are replicated and cached throughout the network. ) and Mentor Graphics (NASDAQ: MENT) and Debussy debug environment from Novas Software. Hammer supports design sizes of up to 128 Million Gates, and 16 Gigabyte of in-system memory. Hammer is marketed and serviced through a network of direct sales and distributors. In Japan, Hammer is marketed and supported by Marubeni Solutions Corporation. About Tharas Systems Tharas Systems develops and markets high performance verification systems to designers of complex integrated circuits and electronic systems. The Tharas solution leads to significant shortening of the verification cycle; the payoff is material reduction in time-to-market. Hammer(TM) offers a patented, next-generation hardware accelerator for Verilog, VHDL and mixed language simulations with the fastest compile times and run times, while at the same time offering ease of use and debugging capability comparable to that of software simulators. Increasing verification complexity is one of the main challenges of designing complex integrated circuits and systems today. Founded in 1998, Tharas is privately held and funded by venture capital and private investors from throughout the electronics industry. Corporate headquarters is located at 3016 Coronado Drive, Santa Clara, Calif. 95054. Visit Tharas Systems at http://www.tharas.com/. For more specific product information, email info@tharas.com or call 1-408-855-3200. Hammer(R) is a trademark of Tharas Systems Inc. Tharas acknowledges trademarks or registered trademarks of other organizations for their respective products and services. |
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