Teseda Drives DFT Productivity with Teseda WorkBench Software and Teseda V520 Hardware Platform; Teseda WorkBench Unites Design and Test Processes.

Business Editors/High-Tech Writers

Design Automation Conference 2004

SAN DIEGO, Calif.--(BUSINESS WIRE)--June 7, 2004

DAC--Teseda(TM) Corporation today announced the release of two products, the Teseda WorkBench(TM) and the Teseda V520(TM) hardware platform. Previously bundled exclusively with the Teseda V500(TM) Design-for-Test (DFT) validation system, the Teseda WorkBench is already established as the industry's leading DFT productivity software. The Teseda V520 expands upon the convenience and flexibility of the Teseda V500 and joins it as the industry's only IC test systems priced at under $200 per pin.

"We have been extremely gratified by the success our customers have had with the Teseda WorkBench," said Steve Morris, Teseda president and CEO. "Leading IC companies including Sharp, Texas Instruments, and Sanyo have validated their chips' DFT in days -- or even hours -- instead of weeks. Since the Teseda WorkBench is used for test preparation, execution, and debug, we have unbundled the software to allow multiple users to perform these separate tasks in parallel. We have also added many new features so that our customers can get more done in even less time."

"The Teseda V520 extends the application range of our DFT-Optimized V500 Series of engineering test systems," Morris continued. "With its unique Per-Pin Timing architecture, the Teseda V520 accommodates devices with even the most strenuous DFT requirements. And, given the system's compact size and affordability, it is an ideal platform to support failure analysis of a wide range of DFT-enabled chips, accelerating the correction of yield problems."

The Teseda WorkBench provides a DFT-Intelligent(TM) environment for validation, debug, and diagnosis of integrated circuits and tests based on popular structural test methodologies, including DC and AC scan, memory and logic BIST, and IDDQ. By accepting unmodified industry-standard STIL data, writing diagnostics data directly for ATPG tools, and running on popular workstation platforms, integration with all leading DFT tools is easy and complete. Teseda WorkBench's sophisticated data views help engineers correlate test results with internal device structures for rapid identification and isolation of problem areas.

The Teseda V520's DFT-Optimized(TM) architecture provides the industry's most cost-effective test capability for DFT-enabled devices. The system occupies approximately one square foot (.1 m2) of space and weighs less than nine pounds (4 kg), and is so quiet it integrates unobtrusively in an office or lab environment. Nonetheless, with Per-Pin Timing (PPT), data rates to 50MHz, clocks to 700MHz, and a total of 348 pins with 32 million vectors behind each pin, the Teseda V520 is fully capable of handling many of the most complex chips and advanced DFT constructs.

Pricing and Availability

Both the Teseda WorkBench and the Teseda V520 are successfully completing beta test at a major U.S. integrated device manufacturer (IDM) and at a U.S. fabless semiconductor manufacturer. A single seat of the Teseda WorkBench sells for $35,000 and the Teseda V520 hardware unit is also $35,000. The Teseda WorkBench and the Teseda V520 can be purchased as a bundle for $65,000. Alternatively, both products are available by subscription (time-based license). The Teseda WorkBench and the Teseda V520 are both shipping now.

About Teseda Corporation

Teseda Corporation is the leader in Design-for-Test (DFT) productivity tools that help semiconductor companies dramatically reduce test cost and cut weeks from time-to-money. Teseda is headquartered in Portland, Ore. For more information about Teseda and its products visit www.teseda.com.

Teseda, the Teseda logo, Teseda V500, Teseda V520, Teseda WorkBench, DFT-Optimized, DFT-Focused, and DFT-Intelligent, are trademarks of Teseda Corporation. All other trademarks are property of their respective owners.