Teradyne's RA/PLUS optimizes repairable yield of 64M, 256M and 1G DRAMs with minimal run time.

SEOUL, Korea and AGOURA HILLS, Calif.--(BUSINESS WIRE)--Jan. 24, 1996--Teradyne Inc. Wednesday announced the introduction of RA/Plus, a new intelligent redundancy analysis (RA) algorithm that provides an exact, once-through repair solution.

Part of Teradyne's TerAnalysis RA package and available as an option for all J990 Series memory test systems, RA/Plus is a major step forward that optimizes yield and minimizes test run time for 64 megabit (M) as well as emerging 256M and one gigabit memory chips. Teradyne will be demonstrating RA/Plus on the J995 memory test system here at SEMICON/Korea.

"Teradyne has a long history of leadership in redundancy analysis and repair," said Glenn Farris, J990 product manager. "Device suppliers worldwide told us existing algorithms would not meet their needs for 64M and future generations of dynamic random access memory devices. We developed RA/Plus in response and are proud to once again set a new standard for redundancy analysis."

RA/Plus is a fast, exact, once-through algorithm comprised of a scheduler and pattern analyzer. It always generates the optimum solution for any repairable random access memory (RAM) and does this in a single pass. "Other approaches prevalent in the industry either sacrifice speed or compromise precision by failing to find an existing solution," Farris noted.

Teradyne used actual wafer failure data accumulated by a major memory chip manufacturer and compared two alternative methods (the industry standard "Most Repair" algorithm and a comprehensive algorithm) with Teradyne's new RA/Plus algorithm. The sample consisted of several thousand devices, each with many large and complex redundancy regions.

"In every case, RA/Plus found a solution whenever one was possible," Farris said. "Compared to the comprehensive method, RA/Plus proved to be at least 25 percent faster for the vast majority of devices--and for some particularly difficult examples up to 2,000 times faster." A fast, but approximate approach, "Most Repair," produced variable results. It failed to find the solution for four percent of the repairable regions tested.

RAMs and RA

RAMs generally contain active arrays of memory cells plus spare rows and columns for memory repair. These spare elements are grouped in row and column domains. When failure cells are located in the RAM at wafer probe, the subsequent repair process consists of swapping rows or columns until all failures have been replaced, in which case the memory is repaired.

If all spares are consumed, but failures still remain, then the memory is declared irreparable. As memory devices increase in density and architectural complexity, conventional RA methods become inadequate due to slowness (the "All Repair" or other comprehensive algorithms) or inaccuracy reflected in yield loss (the "Most Repair" algorithm).

RA/Plus is available as part of the TerAnalysis option for J990 Series memory test systems in March 1996. Pricing is under $15K (typical) per test computer.

Teradyne Inc., with headquarters in Boston, is a leading manufacturer of automatic test equipment and connection systems for the electronics and telecommunications industries. Its stock is traded on the New York Stock Exchange under the symbol TER. Address on the World Wide Web is http://www.teradyne.com. Teradyne Inc. reported sales of over $1 billion in 1995.

Note to Editors: RA/PLUS is a trademark of Teradyne Inc. White paper and brochure available upon request, please call Penny Capra, Shafer Public Relations, at 714/863-3213.

CONTACT: Shafer Public Relations

Judith G. Kahn/Penny Capra, 800/503-1177