Teradiant takes SI in stride with sequence's Cooltime.

To reduce time to market for a family of advanced networking silicon, Teradiant Networks built a "single-pass" design flow from best-in-class EDA vendors, and selected Sequence Design's CoolTime for signal-integrity signoff.

"The need for SI analysis is significant," according to Teradiant director of engineering, Chakki Kavoori. "Below 130 nanometers there is cross-coupling all over the chip, and with CoolTime we can readily determine which ones affect performance and target them for corrective action."

Using Sequence for final signoff does not extend time to market since the tool enjoys extremely fast runtimes, typically five to 10 times faster than competing products, and large capacities. It was also a simple matter to integrate CoolTime-SI within Teradiant's existing flow thanks to tight links between Sequence and mainstream EDA tools.

In addition to crosstalk-induced delay and glitch, CoolTime accounts for voltage-drop induced delays during timing analysis. CoolTime renders a complete timing and signal-integrity capability that accounts for on-chip and off-chip physical effects. With a built-in characterization engine for derating delays for voltage drop, CoolTime augments existing timing library formats for accurate timing analysis. An SDF output with voltage drop and crosstalk induced delays can be generated from CoolTime for signoff timing analysis.

CoolTime augments and complements the user's installed physical implementation flow for fast, full-chip signoff of hierarchical SoC designs by eliminating the need for multiple analysis tools and multiple iterations. CoolTime shares a common platform with Sequence's PhysicalStudio for pre- and post-route optimization of timing and signal integrity, thereby enabling fast and accurate design closure for nanometer SoC designs.