Teradiant Networks Releases Family of Traffic Manager Chips for Core, Edge, Metro and Enterprise Networks.

Business Editors/High-Tech Writers

NPC West

SAN JOSE, Calif.--(BUSINESS WIRE)--Sept. 17, 2003

Teradiant Networks, Inc.

-- Offering versions for 10Gbps-40Gbps, deep channelization, and

the most extensive QoS feature set available, Teradiant

enables a new-generation of highly integrated chips for

routers and switches

-- First-ever chip combining 40Gbps traffic manager and switch

drives development of low-cost, QoS-based "pizza box" systems

for metro networks

Teradiant Networks, Inc., a leading developer of silicon solutions for next-generation networks, today became the first vendor to announce availability of traffic manager chips offering 40Gbps aggregated bandwidth. The TeraPacket(TM) family includes two versions of full-featured, super-pipelined traffic managers that provide line-rate performance for the entire suite of network protocols under all network conditions. TeraPacket TM is designed for high-density linecards in systems that utilize switch fabric, and TeraPacket TMS is designed for high-density, single-card systems that do not require separate switch fabric. With the announcement, Teradiant becomes the first provider of a family of traffic managers to offer chips for 10Gbps through 40Gbps applications, and also becomes first to provide traffic manager chips (TeraPacket TMS) that incorporate on-chip switching at 20Gbps and 40Gbps.

"TeraPacket successfully addresses the twin issues of density and performance that face today's linecard and system designers," said Bob Wheeler, senior analyst with The Linley Group, a Mountain View, California-based firm that provides strategic analysis of networking silicon. "Using a pipelined architecture built for speed in processing packets, frames and cells, TeraPacket delivers an unprecedented four 10Gbps channels per chip, combined with an extensive feature set."

Expands the Applications of Traffic Manager Technology

Besides their ability to provide wire-speed performance for IP/MPLS-based and ATM-based routers and switches, TeraPacket traffic managers allow network operators to offer Ethernet-based services over IP/MPLS-based and SONET and SDH-based networks. Therefore, TeraPacket becomes an enabling semiconductor for the large installed base of SONET/SDH networks throughout the world. Similarly, TeraPacket is an ideal solution for network operators in Asia Pacific markets and other areas of the world in which Ethernet is the emerging public-network infrastructure.

TeraPacket is also first to make QoS (quality of service) guarantees a reality for enterprise networks. Although price sensitivity has traditionally ruled out the deployment of QoS mechanisms in the enterprise, the introduction of TeraPacket TMS offers a breakthrough solution for high-end enterprise networks. "TeraPacket's integration of high bandwidth and extensive traffic management features at a low cost-per-Gbps allows network OEMs to incorporate QoS affordably into enterprise and metro networks," said Subhash Bal, Vice President of Marketing and Sales for Teradiant.

Overcomes Limitations of Existing Traffic Manager Architectures

Teradiant has addressed three key challenges that until now forced designers to use multiple traffic manager devices optimized for separate features:

Memory design. Designers have traditionally been hampered by traffic manager architectures that required a significant number of high-speed memory chips for various target applications. Teradiant designed TeraPacket for optimal use of high-speed memory regardless of the application, enabling less complex designs, lower memory-chip count, and reduced memory cost, footprint and power consumption.

Support for different-size packets. Because SONET and Ethernet applications require support for different packet sizes at line rates, traffic manager chips that are limited in the packet sizes or data rates they support also impose a number of design limitations. TeraPacket supports all packet sizes and provides wire-speed performance regardless of the type or size of packet incurred.

Support for a variety of queue and bandwidth requirements. TeraPacket offers support for 16K queues, enabling designers to use the chip for applications as diverse as high-end enterprise switches with a large number of VLANs and lower-bandwidth queues, and core routers, which typically incorporate fewer high-bandwidth queues.

Architected for Applications From "Pizza Box" Systems To Terabit Chassis-Based Systems

The breadth of TeraPacket's speed and feature set makes possible a variety of highly integrated, bandwidth-dense systems -- from low-cost fabric-less 40Gbps "pizza box" systems to terabit chassis-based systems.

Bandwidth density. TeraPacket's unique ability to provide 40Gbps of aggregated bandwidth on a single chip makes possible a new density in switches and routers. For example, a 160Gbps NPU-based core router incorporating eight 20Gbps duplex TeraPacket TM chips can be built with less than half the number of chips required by competing solutions, enabling an extremely price-competitive, high-density, low-power system. Or, a single-card system that uses TeraPacket TMS both to route traffic and provide switching eliminates the need for discrete switch-fabric chips, making possible a 40Gbps duplex system using two 20Gbps network processors (NPUs), one 40Gbps duplex TMS chip, a CPU, and associated I/O components.

Multiprotocol support. Because TeraPacket is protocol-agnostic, it handles all types of traffic -- Ethernet, SONET, ATM, frame relay, IPv4, IPv6, and MPLS. This broad protocol support makes TeraPacket equally adept at handling Ethernet traffic for switches and routers in enterprise and metro applications, and at handling ATM, frame-relay, and IP/MPLS traffic in edge and core systems.

Deep channelization for SONET infrastructure. TeraPacket supports 256 channels per chip, and channelization down to STS-1 levels. Deep channel support meets the demands of enterprise, metro and similar applications that need to aggregate multiple individual streams of traffic. TeraPacket's channelization capability also makes it a valuable solution for MSPP platforms supporting Ethernet-over-SONET applications, and for POS applications in existing SONET network infrastructures.

ATM-like QoS options for IP networks. TeraPacket enables designers to configure on-chip schedulers and rate limiters to make possible a vast range of quality-of-service (QoS) options. This capability, along with an extensive set of statistics stored on-chip, enables a service provider with a TeraPacket-based system to provide customer-specific QoS guarantees. As a result, designers employing TeraPacket can incorporate differentiated services into IP switches and routers.

Configurability. TeraPacket requires no microcoding, and therefore eliminates the need for complex or lengthy software development cycles. Easily configurable options built into TeraPacket and selectable from a control processor provide the flexibility required to customize TeraPacket to the target application, or to revise an existing design.

Standard interfaces for easy integration with NPUs and switch fabrics. Because TeraPacket uses standard interfaces such as SPI-4.2 and NPSI, it integrates easily with NPUs, ASIC processors, and switch fabric chips. As a result, TeraPacket can be rapidly deployed on new NPU- or ASIC-based linecards or systems, or in upgrades to existing systems. This ability to "mix or match" components eliminates dependency on single-vendor semiconductor solutions and enables designers to maintain their investment in existing applications and software.

Scalability. Offering 10Gbps to 40Gbps TM products, the design of TeraPacket enables a TeraPacket-based system to scale easily to higher bandwidths, making it ideal for highly compact "pizza box" systems, service cards, and large chassis-based systems alike. Because all TeraPacket chips use the same device drivers and APIs (application programming interfaces), it is easy to reuse existing software and knowledge for a smooth migration to higher-bandwidth applications.

Development Support

The TeraPacket family is backed by an extensive range of support hardware and software for design and development. The TeraPacket Reference Blade provides a full-featured, interoperability-tested TeraPacket-based line-card incorporating two 10Gbps channels. Also fully tested with commercially available switch fabrics (CSIX and NPSI), the blade provides a complete development environment for TeraPacket applications.

Teradiant also offers the TeraPacket Software Development Kit (SDK), which includes all required Teradiant APIs, device drivers, and complete documentation. APIs and drivers are portable across different platforms.

Pricing and Availability

TeraPacket is available now in versions optimized for Ethernet (part numbers with the suffix "E"), and in versions optimized for SONET (part numbers with the suffix "S"). Specifications are as follows:

   TeraPacket                           Pin Count          Power
    Part No.         Description         (FCBGA)            (W)
---------------- ------------------- ---------------- ----------------
     8250-E          1x10Gbps TM           1370              12
     8250-S          1x10Gbps TM           1370              12
     8450-E          2x10Gbps TM           2112              18
     8450-S          2x10Gbps TM           2112              18
     9250-E          2x10Gbps TMS          1370              12
     9250-S          2x10Gbps TMS          1370              12
     9450-E          4x10Gbps TMS          2112              18
     9450-S          4x10Gbps TMS          2112              18

Prices range from $645 to $1,645. Prices quoted are for 1-10 units, and volume discounts are available.

Teradiant maintains partnerships with leading NPU and switch fabric vendors as a means of guaranteeing interoperability with those vendors' devices. At Network Processors Conference West, Teradiant will demonstrate a variety of system solutions incorporating TeraPacket with selected NPUs and switch fabric chips. See Teradiant at NPC West, Booth 404, Parkside Hall, San Jose, CA, on October 21-23, 2003. For more information, contact the Teradiant sales department at 2835 Zanker Road, San Jose, CA 95134. Telephone [phone] or fax [phone].

About Teradiant Networks

Teradiant Networks develops and markets semiconductors that enable networking system manufacturers to build scalable switch and router platforms for next-generation core, edge, metro and enterprise networks. In February, 2001, Teradiant raised over $26 million in first-round funding from Menlo Ventures, Idanta Partners, Diamondhead Ventures, FBB, and private investors. For more information, visit www.teradiant.com or call 408-519-1700.

(TM) Teradiant and TeraPacket are trademarks of Teradiant Networks, Inc.