Tensilica claims Xtensa processor beats all other processor cores.

Tensilica, Inc., a provider of configurable and extensible processors, recently announced that the Xtensa V processor core has posted the highest scores ever recorded for a licensable processor core on four key benchmark suites performed by the Embedded Microprocessor Benchmark Consortium (EEMBC): Consumer, Telecom, Office Automation and Networking. The benchmark scores, independently certified by the EEMBC Certification Laboratories (ECL), represent the performance of embedded microprocessors in a variety of real-world applications. The tests confirmed that the Xtensa V processor delivers performance that is from 40 percent better to nearly 8.5X that of any other competitor on each of the four tests using a standard "Out-of-the-box" processor configuration. When optimized versions of the Xtensa V processor were tested, the results were up to 33X the closest competitor.

"The EEMBC benchmarks prove that Tensilica's configurable and extensible processor architecture delivers breakthrough features and optimized performance in embedded devices," said Chris Rowen, president and CEO of Tensilica. "Our new Xtensa V processor not only continues to outperform the competition, but also delivers an architecture that significantly reduces design time and complexity. As the only configurable and extensible processor supplier to provide comprehensive and automatic software, modeling and EDA support, Tensilica enables the delivery of optimized, customized processors in hours, as opposed to months."

Tensilica's processor generator technology creates a complete, correct-by-construction processor solution--hardware, software environment, modeling and EDA tools--in just over an hour. Each core can be optimized for virtually any application. Changes made by the user to extend the Xtensa processor hardware--adding instructions, registers, processor state and custom execution units--are immediately and automatically reflected in the entire software tool chain, significantly reducing design complexity and time-to-market. By comparison, competitive architectures either prohibit designer-defined extensions or require the designer to manually adjust compilers, assemblers, debuggers, operating systems, instruction set simulators, co-verification models and EDA implementation scripts when user-defined hardware changes are made to the processor RTL.