Tensilica Xtensa LX Processor Tops EEMBC Networking 2.0 Benchmarks; Xtensa LX Beats PowerPC Full-Chip Results.

SANTA CLARA, Calif. -- Tensilica(R), Inc., the only company to automate the design of optimized application-specific configurable processors for system-on-chip (SOC) design, today announced that it has achieved the highest score ever reported on the Networking Version 2.0 benchmark suite of the Embedded Microprocessor Benchmark Consortium (EEMBC(R)). Tensilica's Xtensa(R) LX processor is the first licensable processor core to complete certification on this challenging benchmark suite.

EEMBC benchmark scores, based on simulation, show that an optimized Xtensa LX processor core is significantly faster on a per-MHz basis than the only two other processors certified to date, the 1GHz PowerPC(R) 750GX and 1.4 GHz PowerPC MPC7447A, both of which are full-chip, standard product processors. The Xtensa LX processor delivers this outstanding performance while simultaneously delivering a 4X code density advantage and more than a 100X advantage in both die area and power dissipation.

EEMBC Results

The normalized (per MHz) EEMBC TCPmark test scores are:

--1.62434 -- Xtensa LX Optimized

--0.4671 -- PowerPC 760GX

--0.5856 -- PowerPC MCP7447A

--0.33762 -- Xtensa LX Out of the Box

The normalized (by MHz) EEMBC IPmark test scores are:

--0.82138 -- Xtensa LX Optimized

--0.2861 -- PowerPC 760GX

--0.1818 -- Xtensa LX Out of the Box

--0.1751 -- PowerPC MCP7447A

(Because EEMBC scores for licensable synthesizable processors, such as the Xtensa LX, are expressed on a "per-MHz" basis, the PowerPC results were normalized to a "per-MHz" basis for this comparison.)

With the Networking 2.0 benchmark, EEMBC simulates real-world networking performance with many different users and differing traffic types. The TCPmark represents processor performance in Internet-enabled, client-side devices. The IPmark represents processor performance in network routers, gateways and switches.

The total code size (aggregate total of bytes of object code) for all twelve benchmark kernels in the Networking Version 2 suite are

--65208 bytes -- Xtensa LX Optimized

--67256 bytes -- Xtensa LX Out of the Box

--255,764 bytes -- PowerPC 760GX

--280,984 bytes -- PowerPC MCP7447A

How Tensilica Achieved These Outstanding Results

Tensilica used two innovative features of its Xtensa LX processor architecture to achieve these outstanding results. First, Tensilica made extensive use of custom FLIX (Flexible Length Instruction Xtensions) instructions including seven different 64-bit instruction word formats with up to eight parallel operation slots. FLIX delivers VLIW-style parallel execution without the "code bloat" typically incurred by VLIW-style processors. In fact, the dramatic 4X to 5X speedup achieved by the Optimized Xtensa LX score versus the Out of the Box Xtensa LX score was accompanied by a decrease of total code size of nearly 2%.

Second, Tensilica selectively employed user-defined TIE (Tensilica Instruction Extension) Queues to dramatically accelerate the IP packet check kernels. TIE Queues allows SOC designers to bypass the standard processor bus and directly import data into the execution units of an Xtensa LX processor, much in the same way that a dedicated hardware accelerator block would process data in an SOC design. Whereas conventional processors are limited to a maximum data throughput of one 32-bit or 64-bit data read or write every clock cycle, Xtensa processors with Queues can sustain data rates of one transfer every clock cycle for every Queue port, with a user-defined bandwidth of up to 1024 bits per cycle. Tensilica's Xtensa LX processor is the only processor that allows designers to bypass the conventional processor-bus-bottleneck in this way. With Tensilica's patented technology, the Queue interfaces and custom packet-header inspection instructions can be added to a processor within hours, complete with fully verified RTL and software tools and models.

About EEMBC

EEMBC, the Embedded Microprocessor Benchmark Consortium, develops and certifies real-world benchmarks and benchmark scores to help designers select the right embedded processors for their systems. Every processor submitted for EEMBC benchmarking is tested for parameters representing different workloads and capabilities in communications, networking, consumer, office automation, automotive/industrial, embedded Java, and microcontroller-related applications. With members including leading semiconductor, intellectual property, and compiler companies, EEMBC establishes benchmark standards and provides certified benchmarking results through the EEMBC Certification Labs (ECL).

About Tensilica

Tensilica was founded in July 1997 to address the growing need for optimized, application-specific microprocessor solutions in high-volume embedded applications. With a configurable and extensible microprocessor core called Xtensa, Tensilica is the only company that has automated and patented the time-consuming process of generating a customized microprocessor core along with a complete software development tool environment, producing new configurations in a matter of hours. For more information, visit www.tensilica.com.

Editors' Notes:

--Tensilica and Xtensa are registered trademarks belonging to Tensilica, Inc. All other company and product names are trademarks and/or registered trademarks of their respective owners.

--Tensilica's announced licensees include Agilent, ALPS, AMCC (JNI Corporation), Astute Networks, ATI, Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, Cypress, Crimson Microsystems, ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, Hughes Network Systems, Ikanos Communications, LG Electronics, Marvell, NEC Laboratories America, NEC Corporation, NetEffect, Neterion, Nippon Telephone and Telegraph (NTT), NVIDIA, Olympus Optical Co. Ltd., sci-worx, Seiko Epson, Solid State Systems, Sony, STMicroelectronics, Stretch, TranSwitch Corporation, and Victor Company of Japan (JVC).