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Tensilica Says Industry On Road to a ``Sea-of-Processors'' As SOC and Microprocessor Development Worlds Converge.


Business Editors/High-Tech Writers

SANTA CLARA Santa Clara, city, Cuba
Santa Clara (sän`tä klä`rä), city (1994 est. pop. 217,000), capital of Villa Clara prov., central Cuba.
, Calif.--(BUSINESS WIRE)--Oct. 17, 2001

CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board.  Chris Rowen row·en  
n. New England
A second crop, as of hay, in a season.



[Middle English rowein, from Anglo-Norman rewain, variant of Old French regain : re-, re- +
 To Unveil Industry Vision

at Microprocessor Forum 2001

Tensilica(R) Inc. will today describe the inevitable, fundamental shift that is expected to occur in microprocessor and System-on-Chip (SOC) development in the coming decade at "Microprocessor Forum 2001." In a keynote speech keynote speech
n.
See keynote address.

Noun 1. keynote speech - a speech setting forth the keynote
keynote address

keynote - the principal theme in a speech or literary work
 entitled "Bridging the Microprocessor -- SOC Design Gap," Tensilica's CEO, Dr. Chris Rowen, will outline the rising need for processors that can be easily customized and optimized for specific applications, as well as seamlessly integrated onto SOC devices. This impetus will drive the industry away from standard, fixed instruction set processors and traditional sea-of-gates ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor.  approaches. Dr. Rowen's "Sea of Processors?" vision will be presented this evening at 5:30 p.m. at the Fairmont Hotel in San Jose San Jose, city, United States
San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850.
, Calif.

"Today's standard, fixed instruction set processors cannot be optimized for their target applications unless designers invest immeasurable resources into developing accompanying complex ASIC blocks," explains Dr. Rowen. "This process is not only time-consuming and costly, but is also completely impractical for SOC designs with multiple processors. The industry needs a microprocessor environment that enables customers to combine both standard functions and their own customized logic onto the processor. Moreover, by automating this process, designers will have a smooth path to multiprocessor integration on SOCs."

Automation Required to Achieve a "Sea of Processors"

Dr. Rowen believes the industry needs a development environment that enables customers to tailor the CPU CPU
 in full central processing unit

Principal component of a digital computer, composed of a control unit, an instruction-decoding unit, and an arithmetic-logic unit.
 for their target application, adding their own customized instructions as needed as needed prn. See prn order.  to the processor, and alleviating the need for complex ASIC solutions. Furthermore, this process must be fully automated, allowing designers to generate their desired CPU at virtually the click of a button.

The end result will be a microprocessor/SOC design world that maximizes chip real estate and dramatically reduces design time. Dr. Rowen's presentation will outline five stages of design enlightenment that are expected to occur in the microprocessor and SOC design process. These stages include:
-- Stage One: System OEMs operating at the first evolutionary stage do not
employ ASICs or SOCs due to the high cost of EDA tools and non-recurring
engineering (NRE) costs, as well as the lack of sophisticated technical
knowledge needed to design SOCs. These companies purchase off-the-shelf
integrated circuits and place them on circuit boards. Chip customization is
limited to burning EPROMs and PLDs. The focus is on board-level design.

-- Stage Two: Designers begin developing primitive SOCs with fixed-architecture
cores. System OEMs at this level often create SOCs by replicating the functions
of existing boards on a chip. Therefore, they use fixed-function duplicates of
processors already used on PC boards. This enables them to work with familiar
processor architectures and to preserve legacy code.

-- Stage Three: Configurable cores come into play. After learning to build
simpler SOCs, system OEMs become ready to start tailoring processors for
applications. The simplest configuration parameters are selectable blocks, such
as floating-point units, and cache sizing (none, 8k, 16k, 32k). The core
processor architecture is not altered, preserving legacy code.

-- Stage Four: Designers begin using extensible processors. Once system OEMs
become acclimated to the idea of customizing processors on SOCs for specific
applications, the next step is to start extending the processor with special
instructions that significantly improve the processor's performance. By making
improvements to certain parts of the code using these new instructions,
designers can achieve as much as 100 times the performance of general-purpose
processors that cannot be optimized for every application. Tensilica's current
product line targets SOC developers operating at this stage of design
enlightenment.

-- Stage Five: Extensibility becomes automated. At this stage, the
microprocessor fades from view. System developers write high-level code in C or
C++ that describes what needs to be done. Development tools analyze this code,
define a processor with instructions that can optimally run the code, and then
compile the C using a specially tailored compiler that uses the tailor-made
processor. Because the tools to support this design approach do not yet exist,
no one currently designs SOCs or systems at this level.


Assessing the Industry: Where are we now?

Dr. Rowen believes that most of the electronics industry continues to operate somewhere between Stage One and Stage Two, and a few companies have started to employ Stage Three design techniques. However, the only way to unlock the full potential of SOC technology is to operate at Stage Five, which gives design teams a practical way of fully realizing the promise of microprocessors, while eliminating the expensive and error-prone ASIC design methods currently in use.

In this future world, individual processors will cost millicents and processor operations will consume femtowatts. In such a world, the total annual processor output could reach 100 billion per year, with 99 percent of all processors shipping as integrated functions on SOCs devices.

About Chris Rowen, Ph.D.

Dr. Chris Rowen is president and chief executive officer of Tensilica. He founded Tensilica in July 1997 to develop and proliferate automatic generation of application-specific microprocessors for communication and consumer systems. He was a pioneer in the development of RISC RISC
 in full Reduced Instruction Set Computing

Computer architecture that uses a limited number of instructions. RISC became popular in microprocessors in the 1980s.
 architecture at Stanford in the early 80s and helped start MIPS Computer See MIPS Technologies.  Systems Inc. in 1984, where he served as vice president for Microprocessor Development. Most recently, he was vice president and general manager of the Design Reuse Group of Synopsys Incorporated. He received a BA in physics from Harvard University Harvard University, mainly at Cambridge, Mass., including Harvard College, the oldest American college. Harvard College


Harvard College, originally for men, was founded in 1636 with a grant from the General Court of the Massachusetts Bay Colony.
 and MS and PhD in electrical engineering electrical engineering: see engineering.
electrical engineering

Branch of engineering concerned with the practical applications of electricity in all its forms, including those of electronics.
 from Stanford University Stanford University, at Stanford, Calif.; coeducational; chartered 1885, opened 1891 as Leland Stanford Junior Univ. (still the legal name). The original campus was designed by Frederick Law Olmsted. David Starr Jordan was its first president. .

About Tensilica

Tensilica was founded in July 1997 to address the fast-growing market for configurable processors and software development tools for high volume, embedded systems Embedded systems

Computer systems that cannot be programmed by the user because they are preprogrammed for a specific task and are buried within the equipment they serve.
. Using the company's proprietary Xtensa Processor Generator, system-on-chip (SOC) designers can develop a processor subsystem hardware design and a complete software development tool environment tailored to their specific requirements in hours.

Tensilica's solutions provide a proven, easy-to-use, methodology that enables designers to achieve optimum application performance in minimum design time. The Company has over 140 engineers engaged in research, development, and customer support from its offices in Santa Clara, Calif.; Burlington, Mass.; Princeton, N.J.; Houston, Texas “Houston” redirects here. For other uses, see Houston (disambiguation).
Houston (pronounced /'hjuːstən/) is the largest city in the state of Texas and the
; Oxford, U.K.; Stockholm, Sweden; Taipei, Taiwan, R.O.C.; and Yokohama, Japan.

Tensilica is headquartered in Santa Clara, Calif. (95054) at 3255-6 Scott Boulevard, and can be reached at 408/986-8000 or via www.tensilica.com on the World Wide Web.

Note to Editors: "Tensilica" is a registered trademark and "Sea of Processors" is a trademark belonging to Tensilica Inc. All other trademarks and registered trademarks are the property of their respective owners.

Tensilica's announced licensees are, in alphabetical order, Berkeley Wireless Research Center, Broadcom, Cisco Systems “Cisco” redirects here. For other uses, see Cisco (disambiguation).
Cisco System,Inc. (NASDAQ: CSCO, HKSE: 4333 ) is an American multinational corporation with 54,000 employees and annual revenue of US $28.48 billion as of 2006.
, Conexant Systems, Fujitsu Ltd., Hughes Network Systems Hughes Network Systems, LLC (HNS), is a provider of broadband satellite network products for businesses and consumers. HNS pioneered the development of high-speed satellite Internet access services and IP-based networks with its original DirecPC service but which it now markets , Ikanos Communications, JNI (Java Native Interface) A programming interface (API) in Sun's Java Virtual Machine used for calling native platform elements such as GUI routines. RNI (Raw Native Interface) is the JNI counterpart in Microsoft's Java Virtual Machine.

JNI - Java Native Interface
.
COPYRIGHT 2001 Business Wire
No portion of this article can be reproduced without the express written permission from the copyright holder.
Copyright 2001, Gale Group. All rights reserved. Gale Group is a Thomson Corporation Company.

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Publication:Business Wire
Geographic Code:1USA
Date:Oct 17, 2001
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