Tensilica Offers Low Cost Development Tools for Diamond Standard Processors; Tools Help Designers Develop Chips With Significantly More Compact Code for Cost-Sensitive Electronic Systems.SANTA CLARA, Calif. -- Tensilica(R), Inc. today introduced a comprehensive software development kit for its Diamond Standard Series processors, a line of off-the-shelf synthesizable CPUs and DSPs (digital signal processors) ready for integration into SOCs (system-on-chip). Priced at just $1,000 for a node-locked license, these tools provide a comprehensive software development kit based on Tensilica's Xtensa(R) Xplorer(TM) development environment, which includes an Eclipse-based GUI (Graphical User Interface) A graphics-based user interface that incorporates movable windows, icons and a mouse. The ability to resize application windows and change style and size of fonts are the significant advantages of a GUI vs. a character-based interface. (graphical user interface graphical user interface (GUI) Computer display format that allows the user to select commands, call up files, start programs, and do other routine tasks by using a mouse to point to pictorial symbols (icons) or lists of menu choices on the screen as opposed to having to ). A key component of the tools suite is Tensilica's advanced C/C C/C Center to Center C/C Combustion Chamber C/C Command/Control C/C Crew Chief C/C cabin cruiser (US DoD) C/C chief complaint (medical) C/C Channel-to-Channel C/C Communication and Collaboration ++ compiler (XCC XCC XML Commerce Connector (Commerce One, Inc.) XCC Expansion Cross-Connect (Module; Eastern Research) XCC Cross Country Competition XCC X.25 Control Center XCC X25 Control Center ). Tensilica's XCC compiler uses aggressive optimization techniques to generate extremely compact code, enabling lower on- and off-chip memory requirements for cost-sensitive electronic systems. "The comprehensive nature of our tool set allows designers to quickly generate compact, high-performance, production quality code for any or all of our Diamond Standard processors," stated Steve Roddy, Tensilica's vice president of marketing. "The tool set also includes a pipeline-accurate instruction set simulator An Instruction Set Simulator (ISS) is a simulation model, usually, but by no means always, coded in a high-level language, which mimics the behavior of a mainframe or microprocessor by "reading" instructions and maintaining internal variables which represent the processor's for all six Diamond Standard processors, which enables rapid development of application code." Tensilica's comprehensive tool set for the Diamond Standard processors includes: --Xtensa Xplorer -- Diamond Edition integrated design environment (IDE) with performance evaluation tools --Pipeline-accurate instruction set simulator (ISS ISS See Institutional Shareholder Services (ISS). ) --Tensilica's Xtensa C/C++ Compiler (XCC) --Complete GNU-based toolchain (assembler, debugger, profiler, linker) --Optimized C libraries for all Diamond Standard cores Xplorer IDE The Xplorer IDE serves as a cockpit for SOC design with Diamond Standard processors. The Xplorer IDE provides a unified environment for C/C++ application software development, code profiling and debugging. It is a visual environment with a host of automation tools that enables rapid code development for complex SOC designs. Instruction Set Simulator Tensilica provides a clock-cycle-accurate, pipeline-modeled ISS matched to each of the Diamond Standard processors. The ISS is fast and accurate, with speeds two or more orders of magnitude faster than RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; (register transfer level) hardware simulation. By accelerating system simulation, Tensilica's ISS decreases overall SOC design time. C/C++ Compiler The XCC Compiler for Diamond Standard processors is an advanced optimizing compiler that provides superior execution performance and smaller size of the compiled code. It provides feedback-directed compilation using profile data collected from the ISS or a target hardware system. The XCC Compiler also provides automatic vectorization for the Diamond Standard 545CK and automatic bundling of operations in VLIW (Very Long Instruction Word) A CPU architecture that reads a group of instructions and executes them at the same time. For example, the group (word) might contain four instructions, and the compiler ensures that those four instructions are not dependent on each bundles for the Diamond Standard 570T, 545CK and 330HiFi. Complete GNU-based Toolchain Tensilica provides a complete GNU-based toolchain with an assembler, debugger, profiler and linker. The GNU software development tools are extremely robust and interface seamlessly with Tensilica's advanced compiler code-generation capabilities. Pricing and Availability Tensilica's tools for the Diamond Standard processors start at $1,000 per year for a single-seat node-clocked license and $2,000 per year for a floating seat license. The tools are available now. About Tensilica Tensilica offers the broadest line of processor cores on the market today, with the six new members of the Diamond Standard processor family plus an infinite number of Xtensa configurable processor possibilities for customers requiring optimized, application-specific solutions. Tensilica's low-power, benchmark-proven processors have been designed into high-volume products at industry leaders in the digital consumer, networking and telecommunications markets. Tensilica also provides industry leading automated tool support for its processor families. For more information, visit www.tensilica.com. Editors' Notes: --Tensilica and Xtensa are registered trademarks belonging to Tensilica Inc. All other company and product names are trademarks and/or registered trademarks of their respective owners. --Tensilica's announced licensees include Agilent, ALPS, AMCC AMCC Applied Micro Circuits Corporation AMCC Air Mobility Control Center AMCC Ashore Mobile Contingency Communications AMCC Advanced Materials Commercialization Center AMCC allied movement coordination center (US DoD) (JNI (Java Native Interface) A programming interface (API) in Sun's Java Virtual Machine used for calling native platform elements such as GUI routines. RNI (Raw Native Interface) is the JNI counterpart in Microsoft's Java Virtual Machine. JNI - Java Native Interface Corporation), Astute Networks, Atheros, ATI, Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, Cypress, Crimson Microsystems, ETRI ETRI Electronics & Telecommunications Research Institute (Korea) ETRI Enhanced Threat Reduction Initiative ETRI Electronics Telecommunication Research Inc. , FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, Hughes Network Systems Hughes Network Systems, LLC (HNS), is a provider of broadband satellite network products for businesses and consumers. HNS pioneered the development of high-speed satellite Internet access services and IP-based networks with its original DirecPC service but which it now markets , Ikanos Communications, LG Electronics, Marvell, MediaWorks, NEC (NEC Corporation, Tokyo, www.nec.com, www.necus.com) An electronics conglomerate known in the U.S. for its monitors. In Japan, it had the lion's share of the PC market until the late 1990s (see PC 98). NEC was founded in Tokyo in 1899 as Nippon Electric Company, Ltd. Laboratories America, NEC Corporation, NetEffect, Neterion, Nippon Telephone and Telegraph (NTT), NVIDIA, Olympus Optical Co. Ltd., sci-worx, Seiko Epson, Solid State Systems, Sony, STMicroelectronics, Stretch, TranSwitch Corporation, u-Nav Microelectronics, and Victor Company of Japan (JVC). |
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