TOSHIBA ANNOUNCES 32-BIT RISC MIPS-BASED MICROPROCESSOR WITH INCREASED PERFORMANCE AND REDUCED POWER CONSUMPTION.

Toshiba America Electronic Components, Inc. (TAEC) with its parent company, Toshiba Corporation (Toshiba) has announced a 32-bit RISC (Reduced Instruction Set Computer) microprocessor for use in battery-powered portable devices.

The new TMP1942 employs a MIPS-based TX19 core that enables high code efficiency and has on-chip read only memory (ROM) and random access memory (RAM) that can be accessed in a single-clock cycle. The TMP1942 integrates an analog system that is enhanced with an integrated high-speed, analog-to-digital converter (ADC) and digital-to-analog converter (DAC), Wakeup Key inputs, 3/5 volt (V) input/output (I/O) port support, and increased timer channels. Toshiba is currently developing an on-chip Flash memory version of the TMP1942 as well.

At 32 megahertz (MHz) the processor consumes only 200 milliwatts (mW) making it best suited for low-power applications in personal mobile devices such as cameras, digital video cameras and other handheld products. Digital devices for handheld use require more functionality, higher performance, and increased battery life while being more compact and lighter weight. These devices are also required to have fewer parts and to consume less power. Toshiba has developed the TMP1942 with an enhanced analog system and expanded peripheral functionality as a new product in the TX19 family of 32-bit TX System RISC processors to meet these customer needs in personal handheld applications.

The TMP1942's high-speed ADC has a 1-microsecond conversion time, and the chip's 3-channel, 10-bit precision DAC with output AMP can readily translate high analog data amounts. This will require fewer external parts with faster response time than if an external filter was attached to the PWM output.

The TMP1942 features two types of ports with independent power pins. These power pins function as 5V I/O pins when a 5V power source is supplied and as 3V I/O pins when a 3V power source is supplied. The 16-bit timer supports a two-phase pulse input count function, which is an ideal interface for a jog dial application. There are 14 wake-up key inputs, which are suitable for applications that use key input to wake a system from standby mode.

The code efficiency of the TMP1942 is 40 percent more efficient than that of previous 32-bit instruction processors. This is achieved by adding extended MIPS16ASE (16-bit instructions) to 32-bit R3000A architecture. Both R3000A and MIPS16ASE are from MIPS Technologies Inc.

In addition to ROM and RAM that can be accessed by a single clock, the processor integrates a 5-channel serial I/O that can be programmed for synchronous and asynchronous serial I/F, a 1-channel Fast Mode I2C to communicate with external LSI peripherals, and versatile 12-channel, 8-bit timers and 14-channel, 16-bit timers. Integrating Flash memory to the product line facilitates easier software debugging since data in Flash memory can be rewritten. The mask version employs a ROM correction function so it is possible to deal with bugs in programs on ROM ported to and developed in the Flash memory version without having to rebuild the mask.

Toshiba and third-party tool venders will provide integrated development environments for this product line. Toshiba will maintain continuity between the development tools for the complex instruction set computer (CISC) microprocessor TLCS-900 series and the TX19, providing a seamless language tool environment. Development tools such as C compilers, debuggers, RTOS and reference boards will be available to customers.

ROM code acceptance for the Mask ROM version of the TMP1942 (TMPR1942CYU/CYXB) is scheduled in Q2 2002. The product is priced at $12 each for 10,000 unit quantity. The Flash version of the TMP1942 (TMPR1942FDU/FDXB) are scheduled to be available in Q1 2002 at a price of $30 each for 10,000 unit quantity. Production of both products is scheduled for Q3 2002. The processor is packaged in a 144-pin low quad flat pack (0.4 mm pitch) or a 177-pin chip scale package (0.8 mm pitch FBGA).