TERADYNE EXPANDS THE INTEGRA J750 FAMILY OF TEST SYSTEMS.

Teradyne's Integra Test Division has announced the new J750k test system with an entry level price of $99,000. The J750k, an expansion to the successful INTEGRA J750 Family of test systems, offers the lowest cost of test for low-end semiconductor devices. The J750k was designed specifically to reduce the cost of test without compromising production efficiency, flexibility or reliability. Available in Q1 2001, the J750k basic configuration starts with 64 pins at 33MHz and can be expanded up to 256 pins at 66MHz. As test requirements increase, the system may be upgraded to higher pin counts and speed with field hardware and software upgrades. The J750k may also be configured with system options, like the mixed-signal or memory test options, to address the variation of testing needs.

With the introduction of the INTEGRA J750 in 1998, Teradyne revolutionized the ATE industry by offering a flexible test solution at an industry leading cost per pin price point. Since then, the market has rapidly accepted the INTEGRA J750 as the most economical solution for testing microcontrollers, FPGAs, ASICS and PLD devices. Today, the Integra Test Division has added new options and capabilities to the system to address other high-volume device markets like smartcards and baseband mixed-signal. Teradyne has accepted over 600 orders for the INTEGRA J750 and has shipped over 500 systems worldwide.

Doug Elder, marketing manager for the Integra Test Division, said, "The J750k targets a whole new market segment for the INTEGRA J750 Family of Test Systems. Where test efficiency and low cost of test are crucial to bringing high volume, low frequency devices to market quickly, the J750k is the most complete solution available today. We offer a proven solution at the lowest price per pin in the industry, without compromising quality and system functionality. The J750k features the same innovative architecture as the J750 family, delivering the best test economics and meeting the production-test challenges of today's high-volume devices. Our customers will appreciate the true cost/performance breakthrough that this series of test systems continues to provide."

The J750k delivers the lowest priced leading edge ATE technology on the market, with all the advantages of the J750 family. The system is 100% software and DIB compatible with the entire J750 family. The J750k achieves over 95% parallel test efficiency and its zero footprint design allows for more efficient use of production floor space to reduce cost of ownership. The system also features IG-XL test software, the semiconductor ATE industry's first test development suite combining the power and performance of the latest PC technology and Windows NT operating system with the familiarity of standard Windows productivity tools, like Microsoft Excel and Visual Basic.

The J750k is available for shipment mid-Q1 2001. U.S. pricing for the J750k starts at $99,000 for a basic configuration of 33 MHz, 64 pin channel board with 1 Meg of memory. The system can be configured with up to 256 pins and may be upgraded to a 512 pin J750 configuration with the purchase of additional hardware and software enhancements.