SyntheSys Research Announces New Capabilities for PCI Express, SATA and SAS Serial Bus Testing.The Latest Editions to BERTScope(TM) Family MENLO PARK Menlo Park. 1 Residential city (1990 pop. 28,040), San Mateo co., W Calif.; inc. 1874. Electronic equipment and aerospace products are manufactured in the city. Menlo College and a Stanford Univ. research institute are there. 2 Uninc. , Calif. -- SyntheSys Research, a developer and manufacturer of high-speed signal integrity test and measurement solutions for the computer, storage, and communications industries, introduces the new BERTScope "B" family of products for testing from 0.1 to 12.5 Gb/s. Serial buses in computer and storage applications have some unique challenges including compliance testing and clocking of test devices. Design engineers testing to the latest PCI Express A high-speed peripheral interconnect from Intel introduced in 2002. Note that although sometimes abbreviated "PCX," PCI Express is not the same as "PCI-X" (see PCI-SIG and PCI-X for comparison). As a result of the confusion, "PCI-E" or "PCIe" is the accepted abbreviation. , Serial-ATA, Serial Attached SCSI See SAS. and Fully Buffered DIMM Fully Buffered DIMM (or FB-DIMM) is a memory technology which can be used to increase reliability, speed and density of memory systems. Conventionally, data lines from the memory controller have to be connected to data lines in every DRAM module. standards can utilize the new BERTScope S 7500B and S 12500B capabilities for accurate compliance testing. To help designers successfully stimulate their devices under test, new features of the BERTScope "B" include * comprehensive range of differential divided clock outputs for supplying test devices with an instrument-grade clock at the sub-rate commonly required to allow testing to be achieved, * the ability to add stress to an externally supplied clock, to allow the test device's own signal to be the source for testing, * stressing of an external clock with Spread Spectrum Clock (SSC SSC Secondary School Certificate SSC Standard Systems Center (USAF) SSC State Services Commission (New Zealand) SSC Swedish Space Corporation SSC Salem State College (Massachusetts) ) present on it to provide realistic test signals. New signal integrity analysis features for BERTScope "B" include * analysis of physical layer parameters such as eye diagrams and jitter A flicker or fluctuation in a transmission signal or display image. The term is used in several ways, but it always refers to some offset of time and space from the norm. For example, in a network transmission, jitter would be a bit arriving either ahead or behind a standard clock cycle with SSC on the input signal, * BER (1) (Basic Encoding Rules) A set of encoding rules for ASN.1 notation, which is a method for defining data structures. See ASN.1. (2) (Bit Error Rate) The average number of bits transmitted in error. See BERT. 1. and eye diagram measurements down to 100 Mb/s, operable operable /op·er·a·ble/ (op´er-ah-b'l) subject to being operated upon with a reasonable degree of safety; appropriate for surgical removal. op·er·a·ble adj. with internal or external clock, * variable depth eye and mask measurements to allow shallow measurements like a sampling scope, and deeper measurements, * active measurement and graphing of BERTScope CR clock recovery loop bandwidth and peaking, for precision compliance verification, * jitter tolerance compliance template testing with margin evaluation and margin limit search, * best in class analyzer input bandwidth in excess of 20GHz for the best accuracy and fidelity physical layer measurements such as jitter. "Our customers have been continually challenged with testing their high-speed serial components, boards, and buses. The BERTScope "B" family offers fast and versatile compliance testing addressing the challenges of serial data buses with spread spectrum clocks," said Dr. Lutz Henckels, Chief Executive Officer of SyntheSys Research. "We are also pleased to offer an expanded feature set for analyzing signal integrity problems, providing more insight into bit errors and saving development time." The flexible BERTScope SPG SPG - System Program Generator. A compiler-writing language. ["A System Program Generator", D. Morris et al, Computer J 13(3) (1970)]. 12500B is available with a stress generator only. An upgrade path from any BERTScope product to the new BERTScope S 7500B and S 12500B is available for the extensive installed base of customers. Availability Delivery for the BERTScope S 7500B Stress Generator and Analyzer (7.5Gb/s), S 12500B Stress Generator and Analyzer (12.5Gb/s) and SPG 12500B Stress Generator only (12.5Gb/s) are 6 weeks ARO. About BERTScope(TM) BERTScope(TM) is a trademark of SyntheSys Research, Inc., a privately held California corporation. Founded in 1989, its mission is to develop advanced test instruments for identifying and locating the source of errors in high-speed digital bit streams. BERTScope pairs with BERTScope CR to offer the vision of a scope, the confidence of a BERT (Bit Error Rate Test) An analysis of network transmission efficiency that computes the percentage of bits received in error from the total number sent. , and clock recovery you can count on. More information is available at www.bertscope.com. |
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