Synplicity Enhances Powerful Identify Debugging Tool; Enhanced Version of Synplicity's Identify RTL Debugger Delivers A Powerful, User-Friendly Debugging Solution.SUNNYVALE, Calif. -- Synplicity Inc. (Nasdaq:SYNP SYNP Synchronization Profile ), a leading supplier of software for the design and verification of semiconductors, today announced an enhanced version of its Identify(R) RTL (Register Transfer Level) A high-level hardware description language (HDL) for defining digital circuits. The circuits are described as a collection of registers, Boolean equations, control logic such as "if-then-else" statements as well as complex event sequences; Debugger software that includes several ease-of-use features, delivering customers the most comprehensive debugging solution in the industry. An important member of Synplicity's product portfolio of FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. design tools, the Identify software combines powerful debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. features with the ease of use that Synplicity customers have come to expect. Enhancements to the latest version of the Identify software include mixed-language support, cross triggering between multiple instances of the Intelligent In-Circuit Emulator See ICE. (IICE IICE Information Integration for Concurrent Engineering IICE Interactive Internet Collaborative Environment (Insoft) (TM)) and signal equivalence capability. Additionally, the debugging solution now offers support for Altera's Stratix II family of FPGAs. With these enhancements to the Identify software, Synplicity believes users will be able to quickly and easily debug their FPGA designs, resulting in a savings of weeks in debugging time. Marty Stainbrook, ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. engineer, Emulex Corporation, said of Synplicity's debugging solution, "The Identify software has enabled us to trim weeks off our debugging time. Our previous method of debugging internal signals on FPGA prototypes was to add probes to the design. This approach resulted in time consuming limitations, including few available pins and unpredictable probe routing delays. Now with the Identify software, we can instrument entire modules in one go, saving a tremendous amount of time. There is no denying the benefits of the Identify software." Synplicity's Easy-to-Use FPGA Debugging Methodology The Identify 2.2 software is closely integrated within Synplicity's FPGA design flow, offering designers an easy, yet powerful debugging solution. Synplicity's Identify Instrumentor software allows designers to annotate annotate - annotation directly in their HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. code the signals and conditions they want to monitor, then seamlessly run synthesis and place-and-route to implement the FPGA device. Once the FPGA has been programmed, the Identify RTL Debugger is run, allowing users to view actual signal values directly in their HDL code and debug a live FPGA, in-system, and at the target operating speed The operating speed of a road is the speed at which motor vehicles generally operate on that road. The precise definition of "operating speed", however, is open to debate. . "The Identify software offers the speed and accuracy of a logic analyzer (1) A device that monitors computer performance by timing various segments of the running programs. The total running time and the time spent in selected program modules is displayed in order to isolate the least efficient code. with the convenience and diagnostic capability of a simulator," said Jeff Garrison, director of FPGA product marketing at Synplicity. "Unlike any other FPGA debug product, the Identify solution allows designers to probe their design and annotate results directly in their HDL source code. We work closely with our customers to maintain an easy-to-use methodology, while supporting powerful triggering capabilities that let designers capture and analyze the exact data they need." The Identify 2.2 software offers more comprehensive features including mixed-language support for customers using both VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. and Verilog modules within their design. The use of mixed-language support within the Identify software eliminates the need for designers to manually re-implement an IP module that is written in a language different from the primary language of the design. The latest version of the Identify software also includes a feature that enables users to cross trigger between IICEs. With the Identify 2.2 software, multiple IICE triggers can be combined into a master trigger that controls the buffer. A master trigger from so many sources across clock domains is a very powerful mode of triggering that allows triggers from an IICE operation in one clock domain to trigger another IICE in another domain. This feature allows users to find timing problems between domains quickly and easily. An additional feature to the Identify 2.2 software is its signal equivalence capability. Currently signal instrumentations do not propagate to different levels of the designs. The signal equivalence feature within the Identify 2.2 software solves that problem by propagating the signal instrumentation throughout the design so that it is visible across all levels of hierarchy. Pricing and Availability The Identify 2.2 software is available now and pricing starts at $15,000 (U.S.). For more information on the Identify software, visit Synplicity at http://www.synplicity.com. About the Identify Software Synplicity's believes its Identify software is the only software tool that allows FPGA and ASIC prototyping designers to functionally debug their hardware directly in their RTL source code. This allows functional verification Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, with RTL designs that is up to 10,000 times faster than RTL simulators and enables the use of in-system stimulus for applications like networking, audio and video, and HW/SW HW/SW Hardware/Software designs. The Identify software allows designers to directly select signals and conditions in their RTL source code for debugging and viewing directly in the RTL source code. The software can also save results in standard VCD See Video CD. VCD - Video Compact Disc format that can be used with most waveform viewers. About Synplicity Synplicity(R) Inc. (Nasdaq:SYNP) is a leading supplier of innovative synthesis, verification and physical implementation software solutions that enable the rapid and effective design and verification of semiconductors. Synplicity's high-quality, high-performance tools significantly reduce costs and time-to-market for FPGA, structured/platform ASIC and cell-based/COT ASIC designers. The company's underlying Behavior Extracting Synthesis Technology(R) (BEST(TM)), which is embedded in its logical, physical and verification tools, and has led to Synplicity's top position in FPGA synthesis, now provides the same fast runtimes and quality of results to ASIC and COT customers. The company's fast, easy-to-use products support industry standard design languages (VHDL and Verilog) and run on popular platforms. Synplicity employs over 280 people in its 20 facilities worldwide. Synplicity is headquartered in Sunnyvale, California Sunnyvale ([sʌniveil]) is a city in Santa Clara County, California, United States. It is one of the major cities that make up the Silicon Valley. As of the 2000 census, the city population was 131,760. . For more information visit http://www.synplicity.com. Forward-Looking Statements This press release contains forward-looking statements including, but not limited to, statements regarding the performance, achievements, benefits and industry position of the latest versions of the Identify software. These statements are only predictions and involve known and unknown risks, uncertainties and other factors that may cause the actual results to differ materially from the forward-looking statements, including the performance and benefits of Synplicity's software relative to relevant industry methods or standards, design flaws, design difficulties or other problems with the enhanced Identify software and the growth and changing technical requirements in the FPGA market. For additional information and considerations regarding the risks faced by Synplicity, see its annual report on Form 10-K Form 10-K A report required by the SEC from exchange-listed companies that provides for annual disclosure of certain financial information. Form 10-K See 10-K. for the year ended December 31, 2004 as filed with the Securities and Exchange Commission, as well as other periodic reports filed with the SEC from time to time, including its quarterly reports on Form 10-Q Form 10-Q See 10-Q. . Although Synplicity believes that the expectations reflected in the forward-looking statements are reasonable, Synplicity cannot guarantee the future performance or achievements of its software. In addition, neither Synplicity nor any other person assumes responsibility for the accuracy or completeness of these forward-looking statements. Synplicity disclaims any obligation to update information contained in any forward-looking statement. Synplicity, Behavior Extracting Synthesis Technology and Identify are registered trademarks of Synplicity Inc. BEST and IICE are trademarks of Synplicity Inc. All other names mentioned herein are the trademarks or registered trademarks of their owners. |
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