Synopsys design-for-test and IBM Microelectronics deliver first-pass silicon success.MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--April 10, 1995-- Synopsys, Inc. (NASDAQ NASDAQ in full National Association of Securities Dealers Automated Quotations U.S. market for over-the-counter securities. Established in 1971 by the National Association of Securities Dealers (NASD), NASDAQ is an automated quotation system that reports on : SNPS SNPS Space Nuclear Power System ) today announced that designers using Synopsys Test Compiler and Design Compiler with IBM Microelectronics high-performance ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. technologies have achieved first-pass silicon success on more than 45 ASIC designs ranging in size from 150K-gates to almost one million gates. Successful customers include companies such as Cray Research, Unisys and 3DO. The Synopsys design-for-test (DFT) solution is available for all IBM process technologies, including the recently announced 0.365 L-effective CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. 5S process. Every one of these designs used IBM's level-sensitive scan design level-sensitive scan design - (circuit design) (LSSD) A kind of scan design which uses separate system and scan clocks to distinguish between normal and test mode. Latches are used in pairs, each has a normal data input, data output and clock for system operation. (LSSD LSSD - level-sensitive scan design ) test methodology, which ensures complete testability of chips with minimal impact on die area and system performance. Synopsys has supported the LSSD methodology since the introduction of Test Compiler in 1991. Designers have used Test Compiler for the wide range of IBM LSSD design styles available in IBM Microelectronics technologies. Synopsys will continue to enhance its support for LSSD-based design over the next year by introducing more sophisticated modeling capabilities. "IBM has some of the industry's highest performing process technologies accompanied by very reliable test methodologies for deep submicron ASICs," said Bill Salefski, director of test at Synopsys. "Synopsys is committed to supporting designers of high complexity chips who require the performance and test capabilities offered by IBM." "We are pleased to have the support of the industry's leading synthesis tool supplier for our new CMOS 5S process technology," said Christine King, ASIC product manager at IBM Microelectronics. "Today, many of our customers use Synopsys' logic and text synthesis tools. Synopsys' plan to support additional IBM Design-For-Test capabilities allows these customers to capitalize on their investment while taking advantage of our advanced test capabilities. The Synopsys test support gives our customers further access to proven tools which support IBM's DFT." Industry Standard DFT Solution Synopsys and IBM provide a complete DFT solution for customers developing designs for production in IBM technologies. Test Compiler performs scan synthesis including intelligent selection and connection of LSSD scan elements, as well as IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. 1149.1 (JTAG) synthesis. Test synthesis using Test Compiler is supported as part of the IBM ASIC design tool kit along with Synopsys' Design Compiler for synthesis, VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. System Simulator (VSS) for design verification and Design Time for timing analysis. For ASIC sign-off, the design kit also includes IBM's EinsTimer static timing analysis tool and IBM's automatic test pattern generation ATPG (acronym for both Automatic Test Pattern Generation and Automatic Test Pattern Generator) is an electronic design automation method/technology used to find an input (or test) sequence that, when applied to a digital tools. Pricing and Availability Synopsys' Test Compiler, supporting IBM's LSSD methodology for the CMOS 4L, 4LP, 5L and 5S ASIC process technologies, is available immediately. Test Compiler pricing starts at $50,000 U.S. list. About the Company Synopsys, Inc. (NASDAQ:SNPS) develops, markets and supports high-level design automation models and software for designers of integrated circuits (ICs) and electronic systems. The company pioneered the commercial development of logic synthesis and test synthesis technology, which serve as the foundation of the company's high-level design methodology. Synopsys offers a comprehensive set of synthesis, simulation, test, and design reuse solutions, which support both Verilog HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. and VHDL. -0- Note to Editors: Synopsys is a registered trademark of Synopsys Inc. Test Compiler, Design Compiler, Design Time and VSS are trademarks of Synopsys Inc. TestBench and EinsTimer are trademarks of IBM. Verilog is a registered trademark of Cadence. CONTACT: Synopsys Inc. Lisa Young, 415/694-1853 VitalCom Scott Seiden, 415/637-8212 |
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