Synopsys Physical Compiler Enables 40% Reduction in Time to Market for NEC Electronics.Business Editors/High-Tech Writers MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Oct. 16, 2001 NEC (NEC Corporation, Tokyo, www.nec.com, www.necus.com) An electronics conglomerate known in the U.S. for its monitors. In Japan, it had the lion's share of the PC market until the late 1990s (see PC 98). NEC was founded in Tokyo in 1899 as Nippon Electric Company, Ltd. Electronics Accepts Placement Hand-Off With Synopsys Physical Compiler to Tape Out Two Low Power Communication ICs Synopsys, Inc. (Nasdaq:SNPS SNPS Space Nuclear Power System ), the leader in implementation technology for complex IC design, today announced that NEC Electronics Inc. has successfully used Synopsys Physical Compiler(TM) to tape out two low-power, 0.18-micron, 1.8-million gate, 100 MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. network switch fabric integrated circuits Integrated circuits Miniature electronic circuits produced within and upon a single semiconductor crystal, usually silicon. Integrated circuits range in complexity from simple logic circuits and amplifiers, about 1/20 in. (1. (ICs). Using Physical Compiler, NEC customer Erlang Technology, a fabless semiconductor company A fabless semiconductor company specializes in the design and sale of hardware devices implemented on semiconductor chips. It achieves an advantage by outsourcing the fabrication of the devices to a specialized semiconductor manufacturer called a semiconductor foundry or "fab. that designs and develops switch fabric components, realized a 40% to 50% savings in turnaround time (1) In batch processing, the time it takes to receive finished reports after submission of documents or files for processing. In an online environment, turnaround time is the same as response time. . Following this successful engagement, NEC Electronics has integrated Synopsys Physical Compiler into its standard design flow for 0.18-micron and lower SOC designs. "The productivity gains from Physical Compiler's use of actual placed gates instead of wireload models are substantial. To have a one-pass timing closure flow using Physical Compiler saves a tremendous amount of time for designers," says Dr. Hitoshi Yoshizawa, vice president of NEC Electronics' communications strategic business unit. "The extensive help from Synopsys contributed to a smooth design flow and helped us avoid unexpected problems later on. With Physical Compiler, we were able to move from a placed gates netlist to tape-out in just five weeks, an excellent industry result." With the adoption of Physical Compiler, NEC Electronics and Erlang were able to realize dramatic performance gains and reduced time-to-market for two network switch ICs designed for the rapidly evolving communications market. Erlang generated placement information along with the synthesized netlist for its handoff to NEC. Afterward, no routing iterations were required for timing closure, which substantially streamlined the design flow. NEC Electronics and Erlang also benefited from the built-in test capability within Physical Compiler to perform scan insertion and stitching. The built-in test capability is available through the integration of Physical Compiler with Synopsys DFT DFT - discrete Fourier transform Compiler. "At Erlang, circuit performance and time to market are extremely important," said Tom McLaughlin, vice president of Business Development, Erlang Technology, Inc. "By using Synopsys Physical Compiler, we were able to improve performance and cut turn around time 40-50% compared to our previous design project flow. It was a clear win for us to incorporate Synopsys Physical Compiler in our standard design flow." "NEC is clearly a leader in high-performance ASICs," said Sanjiv Kaul, senior vice president and general manager of the Physical Synthesis business unit at Synopsys. "Synopsys and NEC have now enjoyed joint customer success worldwide with physical synthesis. We are delighted to be working with NEC on their next-generation flow with placement handoff." About Physical Synthesis With over 250 customer tape outs and dozens of companies standardizing on Synopsys' Physical Synthesis, it has become the de facto [Latin, In fact.] In fact, in deed, actually. This phrase is used to characterize an officer, a government, a past action, or a state of affairs that must be accepted for all practical purposes, but is illegal or illegitimate. solution for designing complex, deep submicron chips. Synopsys' Physical Synthesis overall design flow includes Physical Compiler(TM), Route Compiler standard cell router, Chip Architect design planner, ClockTree Compiler clock tree synthesis and FlexRoute top-level router. About Synopsys Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California For the census-designated place, see Mountain View, Contra Costa County, California. For other places called "Mountain View", see . Mountain View is a city in Santa Clara County, in the U.S. state of California. The city gets its name from the views of the Santa Cruz Mountains. , creates leading electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services support services Psychology Non-health care-related ancillary services–eg, transportation, financial aid, support groups, homemaker services, respite services, and other services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com. Note to Editors: Synopsys is a registered trademark and Physical Compiler is a trademark of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners. |
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