Synopsys Design Constraints SDC Format Achieves Unprecedented Adoption; Ten New EDA Partners Join Company's TAP-in Program.NEW ORLEANS--(BUSINESS WIRE)--June 21, 1999-- Synopsys, Inc. (Nasdaq:SNPS SNPS Space Nuclear Power System ), the design technology leader for complex IC design, today announced that 10 more electronic design automation (EDA (1) (Electronic Design Automation) Using the computer to design, lay out, verify and simulate the performance of electronic circuits on a chip or printed circuit board. ) companies have licensed the Synopsys Design Constraints (SDC SDC Silver Dollar City SDC Security Door Controls SDC Student Development Center SDC San Diego Chargers SDC Science Data Center SDC System Development Charges SDC Studebaker Drivers Club SDC San Diego, California (border patrol sector) ) format by joining the company's technology access program TAP-in (SM). Cypress Semiconductor Cypress Semiconductor is a semiconductor design and manufacturing company. It began operations in 1982 and listed publicly in 1986. Two years later, the company shifted over to the New York Stock Exchange under the symbol, (NYSE: CY). , Frequency Technology, LogicVision, Monterey Design Systems, Sapphire sapphire, precious stone. A transparent blue corundum, it is classified among the most valuable of gems. Sapphires are found chiefly in Thailand, India, Sri Lanka, and Myanmar and also in Australia and in the United States (in Montana). Design Automation, Silicon Metrics metrics Managed care A popular term for standards by which the quality of a product, service, or outcome of a particular form of Pt management is evaluated. See TQM. Corporation, Sonics Inc., Tera Systems and Ultima Interconnect are among the companies that have all recently licensed the popular SDC format, which is used in nearly every multimillion-gate, system-on-a-chip (SoC) design today. With the addition of these new licensees, 23 companies have now joined TAP-in, and together represent over 95 percent of the EDA market revenue, making TAP-in the industry's largest and most widely adopted design format access program. Along with access to the design formats, licensees can receive in-depth training from Synopsys, as well as participate in the important Developers' Forum. SDC allows users the ability to communicate critical "design intent" information between tools at all phases of the design. Designers use one set of constraints to drive synthesis, place and route and verification tools to ensure consistent results throughout the design process. Using SDC, designers can convey one set of consistent timing, area and power objectives to all tools in the design process. This results in more tightly integrated tool interfaces and more reliable design flows. "Synopsys should be commended for taking another leap forward in its drive to standardize stanĀ·dardĀ·ize v. 1. To cause to conform to a standard. 2. To evaluate by comparing with a standard. its design constraints format," said Michel Courtoy, vice president of marketing at Frequency. "This move toward standardization standardization In industry, the development and application of standards that make it possible to manufacture a large volume of interchangeable parts. Standardization may focus on engineering standards, such as properties of materials, fits and tolerances, and drafting will be of tremendous benefit to the users of our design automation tools. Frequency chose to license SDC, since virtually every design carried out today uses constraints from Synopsys. SDC allows our customers to pass constraints through multiple vendors' tools which will increase productivity." As additional companies join the TAP-in program and more formats are exchanged, tool interoperability The capability of two or more hardware devices or two or more software routines to work harmoniously together. For example, in an Ethernet network, display adapters, hubs, switches and routers from different vendors must conform to the Ethernet standard and interoperate with each other. and thus designer productivity will be significantly enhanced. By driving the exchange of technology licenses between EDA vendors, Synopsys is facilitating a more efficient alternative to the formal standardization process. "We are very pleased with the rapid momentum that we have experienced with SDC since its initial announcement at last year's DAC See D/A converter and discretionary access control. DAC - Digital to Analog Converter ," stated Rich Goldman, director of strategic market development at Synopsys. "We feel that this licensing program will significantly benefit EDA companies About Synopsys Design Constraints (SDC) SDC is widely used to describe designer intent for deep submicron designs and include constraints for timing, clock, area, test and power in addition to other environmental and operating conditions. Design constraints drive a variety of EDA tools including synthesis, timing analysis and place and route. They are a key input to logic synthesis The conversion of a high-level electronic circuit description into a list of logic gates and their interconnections, called the "netlist." Every logic synthesis program understands some subset of Verilog and VHDL. -- Synopsys' Design Compiler(TM) and the PrimeTime(R) static timing analysis tool. By providing a common method to describe design intent, Synopsys is addressing the industry's need to simplify the key design challenge of timing closure. Timing constraints, one component of SDC, will allow designers to use the identical constraints to drive synthesis and place and route. This ability to identically interpret design intent should help the place and route tools to realize a design much closer to that predicted by the synthesis tools, reducing costly iterations and accelerating timing closure. About Synopsys' TAP-in Program The TAP-in program was designed to advance EDA tool interoperability through technology exchange and licensing, allowing open and easy access to Synopsys' widely used formats. The basis for TAP-in is to make important formats available quickly with appropriate support and updates. Licensing is open to all interested industry parties, including EDA companies, semiconductor, IP and library vendors, industry organizations and universities. Through TAP-in, partners have access to Liberty(TM) (.lib + STAMP), the most widely-used library format in the electronics design industry today, in addition to the Synopsys Design Constraints format, which was announced at the Design Automation Conference in June of 1998. Both Liberty and SDC are projected to be available in the Spine99 flow, and will offer TAP-in partners another interoperability point to access the spine. Additionally, TAP-in introduced in March of 1999, the VERA VERA Virtual Entity of Relevant Acronyms VERA Virtual Electronic Resource Access VERA Vienna Environmental Research Accelerator VERA Verzeichnis Edv-Relevanter Akronyme (German: Virtual Entity of Relevant Acronyms; website) (TM) test bench automation language, enabling the adoption and evolution of the VERA high-level verification language to improve the productivity and interoperability of verification design environments. Look for additional formats to come. Along with obtaining access to the most widely used standard formats, TAP-in provides its partners with professional support, an open channel to provide feedback, training and focused documentation. About Synopsys Synopsys Inc. (Nasdaq:SNPS), is a leading supplier of electronic design automation (EDA) solutions to the global electronic market. The company provides comprehensive design technologies to creators of advanced integrated circuits Integrated circuits Miniature electronic circuits produced within and upon a single semiconductor crystal, usually silicon. Integrated circuits range in complexity from simple logic circuits and amplifiers, about 1/20 in. (1. , electronic systems and systems on a chip. Synopsys also provides consulting services Noun 1. consulting service - service provided by a professional advisor (e.g., a lawyer or doctor or CPA etc.) service - work done by one person or group that benefits another; "budget separately for goods and services" and support to its customers to streamline the overall design process and accelerate time-to-market. Additional information about Synopsys is available at http://www.synopsys.com. Synopsys is a registered trademark; Liberty, TAP-in, Design Compiler, PrimeTime and VERA are trademarks of Synopsys Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners. |
|
||||||||||||||||

Printer friendly
Cite/link
Email
Feedback
Reader Opinion