Synopsys Advances Physical Synthesis With New Physical Compiler 2.0.

Business Editors/High-Tech Writers

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Dec. 5, 2000

Integrated Power, Structured Datapath and Scan Technologies Enable

Faster Timing Closure in RTL-to-Placed Gates Designs

Synopsys, Inc. (Nasdaq:SNPS) today announced a new version of its premier physical synthesis tool, Physical Compiler 2.0, which provides designers with improved register transfer level (RTL)-to-placed-gates support.

Included are optimization algorithms which provide on average 10 percent better critical path timing and 50 percent better total negative slack (TNS). With Physical Compiler 2.0, Synopsys fully upgrades the complete physical synthesis flow by allowing seamless integration of power optimization, structured datapath synthesis, and scan chain ordering technologies. This provides designers with a single, simultaneous design process that merges logic synthesis with layout design. Physical Compiler's integrated technologies come from Synopsys' Power Compiler(TM), Module Compiler(TM) and DFT Compiler enhanced products.

"Physical Compiler is rapidly becoming a worldwide standard design platform for our DSP and wireless designers," said Mike Fazeli, worldwide electronic design automation support manager for DSP-based designs, Texas Instruments. "Integrating power, test and datapath design capabilities in physical synthesis is an absolute must for us. These features will help us address the growing complexity of our embedded MCU and DSP cores for wireless telecommunications and high-volume consumer applications."

"Integrating our existing power, datapath and test synthesis technologies into Physical Compiler 2.0 further strengthens our physical synthesis offering," said Sanjiv Kaul, senior vice president and general manager, Physical Synthesis business unit, Synopsys. "This in turn helps our customers achieve faster timing closure and improve the overall quality of complex system-on-a-chip designs."

Physical Compiler 2.0 Improves Quality of Results

Physical Compiler 2.0 helps designers increase the quality of results (QoR) in designs using an RTL-to-placed-gates design flow versus a gate-level flow. Improvements to the congestion removal and design rule constraint (DRC) fixing algorithms have resulted in 10 percent average reduction in critical path timing, 50 percent average reduction in TNS, and 20 percent reduction in DRC violations.

"Having successfully taped out one chip at the gate-level using Physical Compiler, we were anxious to take advantage of the RTL-to-placed-gates flow," said Chris Gorzek, senior design engineer, Cray Inc. "In experiments with a 0.12-micron, 450 MHz computing chip, we have seen 15 percent performance improvement over the gate-level flow in some blocks. We are currently using RTL-to-placed-gates flow on an ASIC design."

Physical Compiler 2.0 also offers signal integrity prevention capabilities such as max capacitance, max transition constraint, and improved handling of slew degradation and high fan-out nets.

Power Compiler Reduces Power Consumption, Helps Manage Clock Skew

Fully integrated into Physical Compiler 2.0, Power Compiler provides the industry's first automatic and intelligent placement of clock-gating cells to ensure the lowest power consumption and best possible timing. This intelligent placement of clock-gating cells automatically controls the relative placement of the clock gating elements with respect to the gated registers (flip flops) in order to minimize clock skew and achieve better timing.

Power Compiler's complete power analysis and optimization capabilities are available within Physical Compiler 2.0 helping designers reduce design power consumption by up to 30-60 percent at the synthesizable block level and up to 20-40 percent at the chip level.

Module Compiler Provides Structured Datapath Placement

With Module Compiler's new MC Physical technology, users of Physical Compiler 2.0 can, within a single flow, unify synthesis and placement in datapath designs defined in Module Compiler Language (MCL). The unified flow helps designers achieve improved timing and area by automatically generating and preserving the relative placement of the datapath functions. Using directives in MCL, designers can also specify physical grouping and gate-level tiling for instantiated cells. Additionally, the software allows designers to mix the placement of structured datapath functions with random logic functions defined in RTL (Verilog or VHDL) or MCL, all within the same floorplan.

"Having achieved more than 20 successful design tape outs, virtually all our internal design teams are now using Physical Compiler," said Jean-Pierre Geronimi, Director of CAD, Central R&D, STMicroelectronics. "Given the datapath intensive nature of our designs, and traditional reliance on hand crafting and gate-level tiling to achieve the required performance, we are counting on Physical Compiler's MC Physical technology to increase our designers' productivity. Initial evaluation of the technology shows that we can reach very promising results in terms of density and speed."

DFT Compiler Integrates Test into Physical Synthesis

Integrating DFT Compiler into Physical Compiler 2.0 enables designers to optimize scan DFT without cumbersome scripts and data transfers. The tight integration of scan ordering within physical synthesis helps designers avoid the risks of routing congestion and timing violations that may occur from DFT without physical information. For more information on DFT Compiler, please see http://www.synopsys.com/news/announce/press2000/dft_closure_pr.html.

Pricing and Availability

Physical Compiler 2.0 is available immediately. One-year technology subscription license (TSL) starts at $207,000. Current DC Ultra customers may upgrade to Physical Compiler for $135,000 for a one-year TSL.

About Physical Synthesis

Pioneered by Synopsys, Physical Synthesis helps designers address the challenges of implementing next-generation system-on-a-chip designs. Synopsys' overall design flow includes Chip Architect design planner, Physical Compiler unified synthesis and placement, and FlexRoute top-level router. Synopsys' Physical Synthesis leverages industry-standard tools such as Design Compiler, Module Compiler, PrimeTime(R), Power Compiler and DFT Compiler. Proven interfaces to third-party solutions allow the products to easily plug into an existing design flow.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, Calif., creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Note to Editors: Synopsys and PrimeTime are registered trademarks of Synopsys, Inc. Design Compiler, Module Compiler, and Power Compiler are trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.