Synopsys Adds Swift Interface and Improves Performance of Industry-Leading Model Compiler.

FRANKFURT, Germany--(BUSINESS WIRE)--Oct. 26, 1998--

VMC Release 5.0 Provides High-Performance Models for More Than Thirty

Supported Simulation Environments

The new release of the Verilog Model Compiler (VMC)(TM) from Synopsys Inc. (Nasdaq:SNPS), significantly improves the performance of the industry-leading intellectual property (IP) protection tool and further simplifies the effort required to create robust, portable simulation models directly derived from an IP developer's design flow. VMC Release 5.0 adds a direct SWIFT(TM) interface, making VMC models available for more than thirty simulation environments, including all popular Verilog and VHDL simulators and making it possible to directly port IP created using Verilog for use in VHDL design flows.

In addition to significantly reducing the time it takes to port VMC models, this new direct link also improves the performance of models created with VMC by up to two times. VMC incorporates the Synopsys VCS(TM) simulation engine, the highest performance Verilog simulator available. Recent improvements in VCS' performance further enhance VMC 5.0 models.

VMC protects proprietary information by compiling a Verilog-HDL source code model into a binary object model -- a much more secure method of delivering IP than the alternatives: encryption or non-disclosure agreements. While the object model supports accurate simulation, it cannot be deciphered or reverse engineered. By embedding a sign-off simulator, such as VCS, in the model, all events are executed exactly as they occurred in the original design -- eliminating the risks of other modeling methods that aren't derived from the original design data.

"With the power of its underlying VCS simulation engine, VMC has always provided models that offer uncompromised quality with sign-off accuracy," said John Lenyo, marketing director for Synopsys' Logic Modeling(R) products. "With the addition of a direct SWIFT interface, not only have we been able to significantly improve the performance of VMC models in simulation, we are able to make these models available to designers working in virtually every simulation environment, without requiring any additional effort on the part of the IP developer."

The Logic Modeling SWIFT interface is a simulator-independent API developed by Synopsys and adopted by all major simulator vendors -- including Synopsys, Cadence Design Systems, Mentor Graphics, Model Technology and others -- as an efficient way of linking simulation models to design tools. SWIFT provides consistent model performance across all supported simulators and links models to more than 30 simulation environments including cycle-based simulators. The interface architecture is flexible to allow extension to future interface standards, including the proposed Open Model Interface.

Models Easy to Create, Distribute and Support

Design verification is becoming an increasingly difficult and tedious task, consuming at least half of the typical product development cycle. Successful verification of complex systems and systems-on-a-chip require access to a range of flexible and accurate simulation models of the IP blocks embedded in the design. But, broad model access has historically been limited by semiconductor vendor concerns about both protection and support. Synopsys, through VMC and C ModelFactory(TM), a companion tool for C-based design flows, have helped leading semiconductor vendors, including IBM, Motorola, Siemens and NEC protect their intellectual property, while still making it available to end-user designers.

"Synopsys' industry-leading model compilation technology makes it much easier for us to create and distribute an accurate functional model and it frees us from having to deal with all the issues related to simulator support, version control and model maintenance," said Adam Chen, Director of Technology at PLX Technology. "Synopsys has provided us with a smooth path for creating protected, portable and robust simulation models. This makes it possible for us to rapidly deliver the accurate simulation models our users need to integrate our parts into their designs."

VMC Survives Challenge -- No One Successfully Cracks Secure

Compiler Code and Wins Humvee Vehicle

VMC recently survived a challenge by more than two thousand engineers who checked out Synopsys' Secure IP Challenge website, but were unable to successfully crack VMC's secure compilation technology.

In March, Synopsys first issued a 90-day "Crack the Code, Win the Truck" challenge, offering a Humvee vehicle to the first entrant who was able to successfully recreate a modified DesignWare(R) 8051 microcontroller core modeled using VMC. When no one was able to complete the challenge in the allotted time, Synopsys extended the contest until October 15 to ensure that everyone who wanted to enter had sufficient time to examine the model.

Although no one successfully met the terms of the contest and the protected intellectual property remains secure, Synopsys held a consolation prize drawing from all those who registered and downloaded the model and awarded five digital cameras. The winners are posted on the Synopsys IP Challenge website: http://www.synopsys.com/secureip.

"We've been proclaiming for years that VMC and our related compilation products are the only truly secure way for an IP developer to make simulation models available to end-users -- especially when compared to the alternatives: encryption, which can, and has, been broken and non-disclosure agreements," said Moe Shahdad, product manager for VMC. "With the Secure IP Challenge, we put VMC on the line and it proved that our confidence -- and that of our customers -- in its ability to fully protect IP was fully justified.

Pricing and Availability

VMC 5.0 is available immediately, with prices starting at $45,000 U.S. for users who already have the VCS simulator.

VMC and C ModelFactory are part of Synopsys' powerful, integrated suite of verification products and services, which also includes the industry's fastest Verilog and VHDL simulators, a comprehensive range of proven simulation models, the innovative Eagle(TM) hardware/software co-verification tools and the VERA(TM) testbench automation and analysis products. These tools conform with industry standards to ensure easy integration with customer design environments.

For more information on the Verilog Model Compiler or other Synopsys IP modeling and verification products, check the worldwide web at: http://www.synopsys.com/products/literature/literature.html#hlv, contact your local Synopsys office, email [e-mail], or call 1-800-345-6335.

Synopsys Inc

Synopsys Inc. (Nasdaq:SNPS), is a leading supplier of electronic design automation (EDA) solutions to the global electronic market. The company provides comprehensive design technologies to creators of advanced integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting services and support to its customers to streamline the overall design process and accelerate time-to-market. Additional information about Synopsys is available at http://www.synopsys.com.

Synopsys, DesignWare and Logic Modeling are registered trademarks and Eagle, ModelFactory, SWIFT, VCS, VMC and VERA are trademarks of Synopsys Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.