Synopsys' Formality Supported by Fujitsu With Latest ASIC Libraries; New Libraries Speed Multimillion-Gate SoCs to Market.

Business Editors/High-Tech Writers

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--May 17, 2001

Synopsys, Inc. (Nasdaq:SNPS) today announced that Fujitsu Limited (TSE:6702) now offers their latest ASIC libraries to support Synopsys' Formality(R), the leader in full-chip RTL-to-gate equivalency checking.

To provide mutual customers with a more comprehensive solution for functional verification of multimillion-gate System-on-Chip (SoC) designs, Fujitsu now delivers Formality-qualified Verilog libraries for Fujitsu's CE66, CS66, CE71, CS71, CE81 and CS81 ASIC technologies (0.35, 0.25 and 0.18 micron embedded-array and standard cell processes).

"We are supporting Formality based on customer demand and Synopsys' market and technology leadership in functional verification," said Yoshihiro Tada, Director of Design Methodology, ASIC & System LSI Technology Division, Electronic Devices Group at Fujitsu. "Now our mutual customers will significantly reduce design turnaround time and achieve higher confidence at tapeout."

"Winning the ASIC-library support of a world-class company such as Fujitsu further validates Formality as the best-in-class RTL-to-gate equivalency-checking solution," said Antun Domic, senior vice president and general manager of Synopsys' Nanometer Analysis and Test Group. "This announcement is the first step in our joint efforts to provide our customers with the best functional verification solutions in the industry, and to enable formal verification for functional sign-off in the near future."

About Formality

Synopsys' Formality equivalency checker meets the demand for a faster and more exhaustive alternative to gate-level simulation for functional regression testing. Using formal verification methods, Formality determines functional equivalency by comparing different stages of a design without the need for simulation vectors, permitting designers to rapidly detect implementation errors. Formality's multi-solver architecture enables RTL-to-gate verification of complex multimillion-gate SoC designs in a matter of minutes or hours, instead of the weeks and months typically required by gate-level simulation. Finally, with Formality as an integral part of its verification tool suite, Synopsys provides the fastest and most comprehensive functional verification solution from design concept through implementation.

Synopsys' Complete Functional Verification Solution

Synopsys provides a complete line of functional verification solutions supporting Verilog, VHDL, and mixed-HDL, for complex SoC designs aimed at achieving the highest functional coverage in the shortest amount of time. These solutions include Synopsys' VCS(TM) Verilog simulator, Scirocco(TM) VHDL simulator, VCS/Scirocco-MX mixed-HDL simulation, VERA(R) testbench automation tool, CoverMeter Verilog code coverage analysis tool, DesignWare(R) verification IP, LEDA(R) programmable HDL checker, NanoSim(TM) circuit simulation and Formality equivalence checker.

About Synopsys

Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.

Note to Editors: Synopsys, DesignWare, Formality, LEDA, and VERA are registered trademarks and Nanosim, Scirocco, and VCS are trademarks of Synopsys Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.