Summit Introduces Fourth-Generation Graphical Design Entry Tool; Visual HDL 4.0 improves productivity with open project management, enhanced code generation, and flexible analysis.

BEAVERTON, Ore.--(BUSINESS WIRE)--June 3, 1996--Summit Design Inc. today introduced Visual HDL 4.0, its electronic system design automation (ESDA) tool, with new levels of control and productivity for complex system design entry.

Visual HDL 4.0 includes open project management and revision control to third party frameworks, improved hardware description language (HDL) code generation for higher quality synthesis results, enhanced graphical editors for greater design entry productivity, and improved design analysis and debugging.

"We continue to enhance our graphical design entry tools in response to our customers' requests for increased code control and design flow integration," said Moshe Guy, vice president of marketing for Summit.

"Static state machine analysis and support for third-party simulation further strengthen our next-generation system specification capabilities. Both new and experienced HDL designers have everything they need in this tool to raise their productivity, improve design debugging, and facilitate design reuse."

Through its application programming interface (API), Visual HDL now supports integration with external third-party revision control and design management systems. This enables customers to easily integrate Visual HDL into their proprietary systems built around RCS.

Improved Entry and Code Generation for Synthesis

All of Visual HDL's graphical editors are now equipped with a global visibility command for all graphical and textual information. A new global search and replace command helps replace variable names, strings, or functions throughout the entire design with a single command.

Summit has enhanced Visual HDL's Truth Table and State Machine editors to provide better HDL code generation. The Truth Table editor now features support for several behavioral models and code styles in simulation and synthesis, including clock and reset, generation of CASE statements rather than IF statements, support for a `full_case' synthesis directive, and the ability to control the type of the implicit assignments (blocking or non-blocking) generated by Visual HDL.

The State Machine editor enables designers to generate CASE or IF-THEN-ELSE statements for state diagram transitions. Depending upon the target synthesis tool, this can improve the quality of the synthesis results. Similar improvements have also been made to the code generation for Visual HDL's flow diagrams.

The State Machine editor also provides access to the current state, allowing faster and easier access to internal state machine values to support more powerful and efficient design techniques. Designers can access the current state variable in expressions, control the state registers (name and type), and read the current state value from anywhere in a module's scope.

Flexible Design Analysis and Debugging

Visual HDL's debugging interface has been enhanced to fully support debugging capabilities such as NEXT, STEP and CAUSE & EFFECT with its recently added compiled code simulation engine. To help support system level design and design exploration, Visual HDL's VHDL simulator now supports the input of "C" functions and "C" models for simulation.

Designers can write "C" function calls and use them in Visual HDL's graphical environment. Visual HDL can also use "C" models generated outside the graphical environment.

Visual HDL provides static analysis of state machines which enables checks on expressions defined in the transitions of the state diagrams prior to simulation. Static analysis allows designers to check for and correct design problems such as transition conflicts, unused states or transitions, and redundant or conflicting code which dynamic simulation does not verify.

In addition, Visual HDL's interface for Model Technology's V-System and Mentor Graphics' QuickVHDL simulators is now available. Visual HDL is tightly integrated with these tools for simulation control and debugging. Designers can now leverage the power of Visual HDL's graphical design entry methods with these leading simulators.

Pricing and Availability

Visual HDL 4.0 will be available in the second half of 1996 running on UNIX workstations and Windows-based PCs. Pricing for a floating UNIX license is $30,000 U.S. list. The Windows version is priced at $12,500 U.S. list. Upgrade pricing from Version 3.0 to Version 4.0 is $4,500 U.S. list for the workstation version and $1,800 U.S. list for the PC version. The Visual HDL API is priced separately.

Summit Design Inc. is a leading, international supplier of engineering software products for the creation of electronic systems and integrated circuits (ICs) using top-down design methodologies. The company develops, manufactures and markets tools for design specification entry, design verification and test program generation.

The world's top electronics companies use Summit products to increase engineering and manufacturing productivity, reduce development time and improve the quality of their products. Summit is located at 9305 S.W. Gemini Drive, Beaverton, OR 97008, 503/643-9281. -0-

Note to Editors: Visual HDL is a trademark of Summit. V-System and QuickVHDL are trademarks of Mentor Graphics.

CONTACT: Summit Design Inc.

Daniel Skilken, 503/526-6363

or

VitalCom

Scott Seiden, 415/637-8212

E-mail: [e-mail]