Summit Design Welcomes Doulos To Its Growing ESL And Embedded Systems Training Program; SystemC Users are Able to Exploit the Advanced Debug and Analysis Capabilities of Vista(TM) Across A Full Range of SystemC Training Courses.LOS ALTOS, Calif. -- Summit Design, Inc., a leading provider of electronic system-level (ESL (1) An earlier family of client/server development tools for Windows and OS/2 from Ardent Software (formerly VMARK). It was originally developed by Easel Corporation, which was acquired by VMARK. ) and hardware description language (language) Hardware Description Language - (HDL) A kind of language used for the conceptual design of integrated circuits. Examples are VHDL and Verilog. (HDL (Hardware Description Language) A language used to describe the functions of an electronic circuit for documentation, simulation or logic synthesis (or all three). Although many proprietary HDLs have been developed, Verilog and VHDL are the major standards. ) design solutions, announced today that it welcomes Doulos, the global leader in the development and delivery of world class, market-leading SystemC methodology training, into its rapidly growing ESL & Embedded Systems Training Program. Summit's program, first launched in December of 2005, was developed to simplify and accelerate SystemC adoption. With the addition of Doulos, its 5th program partner and first global training provider, novice and advanced users of SystemC can exploit the special features of Summit's Vista(TM) across the full range of Doulos's SystemC training courses. Doulos is a worldwide provider of industry-leading SystemC training. Selected by the Open SystemC Initiative (OSCI) to author the SystemC LRM LRM Language Reference Manual LRM Casa De Campo, Dominican Republic (Airport Code) LRM Long Range Missile LRM Line Replaceable Module LRM Local Resource Manager LRM Line-Reflect-Match LRM Land Resources Management and IEEE (Institute of Electrical and Electronics Engineers, New York, www.ieee.org) A membership organization that includes engineers, scientists and students in electronics and allied fields. standard, the organization has been actively involved in the development of SystemC methodology training since 2000. More than 100 established and emerging companies across the USA, Asia and Europe have benefited from Doulos' in-house SystemC expertise. "Doulos offers regularly scheduled, as well as customized, SystemC training courses in various locations all around the globe making it possible for engineers following our Transaction-Level Modeling Track to employ Vista to significant advantage," stated Rob Hurley, CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of Doulos. "Vista's Transaction-Sequence Viewer(TM) supports constructs critical to the hardware portion of system-level design and provides advanced analysis of complex SystemC transaction-level models." "Partnering with Doulos -- a worldwide training provider with highly impressive SystemC credentials -- provides excellent value to our customers," said Azeddine Bouchiha, director of SystemC design technologies at Summit Design. "Their impressive curriculum and comprehensive understanding of SystemC, in combination with Vista's robust debug and analysis capabilities, will help to ensure more rapid SystemC adoption and advanced user success." About Doulos Doulos is the global leader for the development and delivery of world class, market-leading training solutions for SoC, FPGA (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. and ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. design and verification. An independent company established in 1991, Doulos sets the industry standard for high quality technical training in SystemC, SystemVerilog, e, PSL 1. PSL - Portable Standard Lisp. 2. PSL - Problem Statement Language. See PSL/PSA. , VHDL (VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. , Verilog, Perl & Tcl/Tk. Doulos in-house expertise and world leading know-how in key technology areas has contributed to the success of more than 600 companies across 30 countries. Regular public courses are scheduled in Europe and the USA while in-house and customised training is delivered world-wide. About Summit's Vista IDE Vista(TM) is an integrated development environment See IDE. integrated development environment - interactive development environment (IDE) for SystemC that combines both hardware and software concepts to speed design and debug of SystemC applications. It is easy to adopt, since it builds upon the industry standard gnu tools. It's unique Data Introspection, design exploration and debugging features make for more rapid understanding of designs and the verification process. Vista also offers advanced coding facilities, browsers, and a verification toolset targeted for high-level SystemC transaction-level modeling (TLM). Vista's SystemC Transaction Sequence Viewer(TM) (TSV) supports effective debug of designs written at the transaction-level, with minimal set-up. With the TSV, designers can automatically view and debug complex communication protocols and system-level interfaces between blocks. While other SystemC design environments require time-consuming manual code instrumentation, Vista's TSV automatically captures the interface method calling sequence and presents the communication protocol transactions in an intuitive tabular format. The unique debugging capabilities in Vista are possible because of its built-in SystemC awareness and its in-depth understanding of SystemC designs. About Summit Summit Design's industry-leading ESL and HDL solutions enable SOC companies to deliver products that meet system-level performance and power targets with dramatically reduced schedule risk. Summit's products address engineering challenges met during the specification and implementation design phases of complex hardware/software systems. System Architect(TM) enables massive increases in design complexity and performance by analyzing architectural tradeoffs to arrive at optimized system specifications. Vista(TM) and Visual Elite(TM) ensure swift, successful design modeling and implementation in SystemC, Verilog, and VHDL. Top electronics companies worldwide, including leaders in the wireless, automotive, and consumer electronics space, have achieved dramatic reductions in design cycle time through their use of Summit's products. Summit Design is headquartered in Los Altos, California Los Altos (IPA: [lɔs ɑltos]) is a city at the southern end of the San Francisco Peninsula, in the San Francisco Bay Area. The city is in Santa Clara County, California, United States. with offices throughout the US, Europe, Japan, Israel, and ROA ROA See: Return on assets ROA See: Right of accumulation ROA See return on assets (ROA). . To learn more, please visit http://www.sd.com. All trademarks or registered trademarks mentioned in this news release are the intellectual property of their respective owners. |
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