Stream Processors, Inc. Announces Storm-1 Family of Data-Parallel Digital Signal Processors.New Class of DSPs Removes Programming Barriers for Parallel Processors and Unleashes Industry-Leading Performance SAN FRANCISCO -- Stream Processors, Inc. (SPI (1) (Stateful Packet Inspection) See stateful inspection. (2) (Service Provider Interface) The programming interface for developing Windows drivers under WOSA. ), a fabless semiconductor company A fabless semiconductor company specializes in the design and sale of hardware devices implemented on semiconductor chips. It achieves an advantage by outsourcing the fabrication of the devices to a specialized semiconductor manufacturer called a semiconductor foundry or "fab. that is making parallel processing simple, today announced the first members of its Storm-1[TM] family of data-parallel digital signal processors (DSPs) - the SP16-G160 and the SP8-G80. Based on the company's breakthrough SPI Stream Processor[TM] Architecture (detailed in a separate announcement issued today and titled "Stream Processors, Inc. Announces Breakthrough Digital Signal Processor Architecture at ISSCC ISSCC International Solid State Circuits Conference ISSCC International Student Services Center Corporation Limited 2007"), the Storm-1 family combines the ability to scale to 80 giga multiplications and accumulations per second (GMACs/s) performance with a simple, predictive and efficient C programming model. The Storm-1 family is suitable for a wide range of demanding signal processing applications, such as high-definition video H.264 HD encoding, transcoding, analytics, image processing and video surveillance with processing headroom for customer-specific enhancements. "Data bandwidth and ease of programming are what matter most in modern computer systems," said Chip Stearns, president and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of SPI. "The level of performance offered by the Storm-1 family will enable a new wave of innovation in markets that have been begging for an easy-to-use path to higher performance without sacrificing software programmability." The SP16-G160 and SP8-G80: A New Class of DSPs The Storm-1 SP16-G160 device is a DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive that offers 160 giga operations per second (GOPS (Giga [billion] Operations Per Second) The measurement of instructional performance of a chip or system. It typically refers to DSP operations. See MOPS. ) and 80 GMACs/s of performance by featuring a high-performance data-parallel unit (DPU) with 16 parallel lanes with five ALUs each. Each ALU (Arithmetic Logic Unit) The high-speed CPU circuit that does calculating and comparing. Numbers are transferred from memory into the ALU for calculation, and the results are sent back into memory. Alphanumeric data are sent from memory into the ALU for comparing. contains a MAC unit and is capable of four 8-, two 16- or one 32-bit operation per cycle. Input and output data for each lane is stored in on-chip lane register files that are allocated by the compiler to maximize data bandwidth. Each device includes a MIPS (Million Instructions Per Second) The execution speed of a computer. For example, .5 MIPS is 500,000 instructions per second; 100 MIPS is a hundred million instructions per second. 32[R] 4KEc[R] CPU CPU in full central processing unit Principal component of a digital computer, composed of a control unit, an instruction-decoding unit, and an arithmetic-logic unit. core for system tasks, and a second MIPS32[R] 4KEc[R] that is dedicated to handling main DSP threads and making kernel function calls to the DPU for acceleration. A rich set of I/O includes Gigabit Ethernet, PCI (1) (Payment Card Industry) See PCI DSS. (2) (Peripheral Component Interconnect) The most widely used I/O bus (peripheral bus). , and high-speed data ports for video and communications. Designed to make parallel performance easily accessible to programmers, a key feature of the architecture is its compiler-managed memory hierarchy and single-threaded approach. A simple C programming model allows specification of compute-intensive kernel functions that process data records, enabling the compiler and hardware to efficiently manage on-chip memory and synchronize runtime direct-memory access (DMA). Kernel functions process stream data in a data-parallel fashion across all of the lanes. Unlike traditional DSPs, there is no need to spend time manually choreographing caches or dealing with synchronization of DMA, or load-balance cores, greatly increasing predictability and simplifying the overall programming task. The Storm-1 SP8-G80 device leverages the SPI Stream Processor Architecture in an eight lane flavor offering 80 GOPS of performance. Additional information about the Storm-1 family can be found at http://www.streamprocessors.com/ Development Tools SPI's RapiDev[TM] tool suite supports an industry standard development and debug flow using C language tools running on a Windows/Cygwin or Linux platform. The RapiDev tool suite includes easy-to-use functional and cycle-accurate simulators and leverages the predictability of SPI's Stream Processor Architecture to provide a fast, linear path to production code. Source code compatibility is maintained across devices with different numbers of lanes and ALUs, providing greater scalability and portability. The Storm-1 Development Kit supports evaluation and software development on SPI hardware, and has I/O options to support multiple video sources and formats, including HD and D1. Price and Availability Priced at $99 for the SP16-G160 and $59 for the SP8-G80 in production quantities of 10,000 units, the Storm-1 family is currently sampling with full production expected in the second quarter of 2007. The chip is housed in a 31x31mm plastic ball grid array “BGA” redirects here. For other uses, see BGA (disambiguation). A ball grid array (BGA) is a type of surface-mount packaging used for integrated circuits. (PBGA PBGA Plastic Ball Grid Array ) and is implemented in 130 nm 1.0 volt standard CMOS (Complementary Metal Oxide Semiconductor) Pronounced "c-moss." The most widely used integrated circuit design. It is found in almost every electronic product from handheld devices to mainframes. process. About Stream Processors, Inc. Stream Processors, Inc. (SPI) is a privately held fabless semiconductor company delivering an innovative stream processing architecture that helps consumer and industrial companies accelerate product development cycles and dramatically reduce system development costs. SPI was founded in 2004 to address the new era of compute-intensive applications requiring radically increased levels of processor performance and power efficiency. The company's technology and products improve application productivity by making parallel processing easier to program and use. Additional information can be found at http://www.streamprocessors.com/. [c] Copyright Stream Processors, Inc. 2007. All rights reserved. Stream Processors, Inc., SPI Stream Processing Architecture, RapiDev, Storm-1 and SPI are trademarks of Stream Processors, Inc. Other product and company names mentioned herein may be trademarks of their respective owners. |
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