Stelar Tools Introduces HDL Explorer to Help Design and Verification Engineers Quickly and Easily Reach RTL Closure.

PORTLAND, Ore. -- First Tool to Offer Combination of Intelligent Design Creation, Exploration, and Editing of Legacy Designs and Testbenches Using Best Known Methods

Stelar Tools(TM), Inc., a venture-backed EDA solutions provider, introduced HDL Explorer(TM), the first EDA tool to deliver rapid RTL Closure. RTL Closure is the process of getting a design clean at the register transfer level, before synthesis, to shorten development time and reduce development cost. HDL Explorer provides a unique combination of new design creation, and exploration and editing of new and legacy designs and testbenches -- all while using best known methods (BKMs). HDL Explorer lets designers and verification engineers quickly and easily find and fix errors, and define and manage the design-verification interface in their new or existing HDL designs. This results in a 30 percent reduction in the time it takes to get a complex ASIC, SoC, structured ASIC, or FPGA design from concept through synthesis. HDL Explorer is the first in a family of products from Stelar that will speed the design, verification, analysis, and testing of complex electronic product designs.

"Because it costs 10 times more to find and fix errors at each successive stage in the design process -- for example, errors found at simulation are 10 times more expensive to find and fix then those caught at RTL, and those found at synthesis are 100 times more expensive -- customers are excited about using HDL Explorer to help them get their designs clean before synthesis," said Steve Sapiro, vice president of marketing, Stelar Tools, Inc. "With HDL Explorer, we've collapsed into one place the hundreds of tasks that must be completed in a large design project. We've made the tool fast and easy to use, and easy to integrate into a project's existing tools and methodologies, enabling users to focus on completing their designs."

New Design Creation is Painful and Error Prone

Designers traditionally spend time manually creating design entities using traditional text editors and exploring existing legacy designs using hard copy printouts and hand-drawn diagrams. Many designers use a simulator or synthesis tools as error checkers and debuggers. And often, design projects must start from ground zero because documentation in today's changing engineering environment is insufficient and knowledge gained from previous projects has been lost or not sufficiently documented. It is important for the project that information is captured and distributed to all members of a design team.

HDL Explorer Speeds RTL Closure for New Designs

HDL Explorer can deliver benefits to designs of every size, but all of its features and thus maximum benefit come into play for designs of two million gates or more. Using five patent-pending technologies, HDL Explorer lets users create new design entities, IP, connections and testbenches, and stitch blocks together. It also enables users to explore and analyze existing designs and testbenches using various views -- helping users quickly find and fix design errors, and to define and manage the design-verification interface. In addition, it offers design managers the ability to easily extract status and statistical information from a large design for better management. With these options, HDL Explorer facilitates rapid RTL Closure to provide a huge time savings over traditional approaches.

Smart Editor Lets Designers Choose Best Methods for Design

Creation

As designs get larger, the text files are substantially larger and harder to deal with using typical text editors. Using a "smart" editor that combines interactive, intelligent text and smart graphics features, HDL Explorer lets an engineer pick the best method for design creation. Users are not forced to choose between text and graphics -- they can easily switch between smart graphical and intelligent text views of a design as needed. The graphics mode enables users to see the big picture, and the intelligent editor enables them to quickly add and connect modules, signals or testbenches through the hierarchy, or to encapsulate a group of modules for later use.

HDL Explorer Speeds Reuse of Legacy Design Elements

Re-using existing legacy design elements, external IP, and testbenches is time-consuming if a designer is not familiar with the design. HDL Explorer facilitates navigation, analysis, and exploration of an existing design, including allowing multiple, different views of the design, to bring designers and verification engineers quickly up to speed on the design's functionality, attributes, characteristics, and behavior.

Use of Best Known Methods Increases Quality and Confidence

HDL Explorer enables design teams to work with BKMs -- bringing a design and design team up to the same, known level of confidence and quality. BKMs help users find and fix errors quickly, and can help implement a company coding style, vendor- or foundry-specific rule set, a technical staff member's design tricks, or an applications engineer's suggestions for customers. BKMs can convert from one design family or style to another, can 'vet' an existing design for conversion to a new process, and can help define and manage the design-verification interface.

Pricing and Availability

HDL Explorer is available immediately worldwide on the Linux and Windows platforms. It can be purchased through Stelar distributors on a per-seat or project basis. Pricing starts at $7,900 (U.S.) for a single-user annual subscription license. Contact Stelar Tools at 503-943-0860 or at [e-mail]

About Stelar Tools, Inc.

Founded in 2003, Stelar Tools, Inc. is a privately-held company that delivers the first true smart graphical and intelligent textual design creation and analysis environment for large, complex HDL designs. This enables designers and verification engineers to rapidly reach RTL Closure by offering them the ability to explore, navigate, analyze, document, and create a design using their current design methodology and tools. Further information about Stelar can be found at www.stelartools.com.

Stelar Tools, Inc, the Stelar logo, and HDL Explorer are trademarks of Stelar Tools, Inc. All other names mentioned are trademarks, registered trademarks, or service marks of their respective companies.

Glossary of Acronyms

    ASIC: Application-Specific Integrated Circuit
    EDA: Electronic Design Automation
    FPGA: Field-Programmable Gate Array
    HDL: Hardware Description Language
    IP: Intellectual Property
    SoC: System-on-Chip
    RTL Closure: Register Transfer Level Closure