Silicon and its future impact on PCBs: a look at coming assembly and packing requirements, based on the ITRS silicon roadmap.

The silicon roadmap, or International Technology Roadmap for Semiconductors, is published every two years, with an update of the Assembly and Packaging chapter published in the NEMI roadmap.

In the most recent ITRS, published last rail, the Assembly and Packaging chapter has been expanded. Many of the most difficult challenges have also been changed to address the needed shifts in research focus. Furthermore, there are new sections on requirements in

* System in package (SiP).

* Substrates technology.

* Materials.

The ITRS does not specifically use emulators or product sectors as do the NEMI and IPC roadmaps but it does recognize product categories that correspond with some of the IPC and NEMI emulators. For 2003 the product categories are:

* Low-cost/Handheld: <$500 consumer products, wireless products, disk drives, and displays.

* Cost-performance: <$3000 notebooks, desktop personal computers, telecommunications.

* High-performance: >$3000 high-end workstations, servers, avionics, supercomputers, most-demanding requirements.

* Harsh: Under-the-hood and other hostile environments.

The most difficult challenges facing the assembly and packaging industry are presented in TABLE 1.

Technology Requirements

Packaging technology continues to change rapidly. Assembly and packaging needs are driven as much by market application requirements as by silicon technology. Cost will drive technology tradeoffs for all market segments.

Chip and package pincount is increasing more rapidly than cost-per-pin is decreasing. This explosion in pin count is increasing not only the absolute cost of assembly and packaging on a per-chip basis, but also the substrate costs. To satisfy the requirements for the increasing numbers of pins needed to leverage silicon productivity more fully, the industry must implement affordable new assembly and packaging technologies that will be more independent of pincount.

Pin count will continue to increase in all segments while die sizes are expected to remain constant, which drives a continuing need for finer off-chip and off-package pitch.

Dramatic improvements in materials properties--to address high frequency, higher power density, and increased mechanical stress--will be required. Major efforts are underway to address environmental concerns such as for lead-free solder assembly implementation and halogen-free materials, and they are expected to continue. Significant new materials research and process development continues to be needed in a number of areas, however. For example, no materials solution is as yet known for drop-in solder replacement for high-temperature (high lead content) applications including Pb-based solder the attach. Additionally, performance indicators such as dielectric constant, dielectric loss and thermal conductivity will be significant to meet higher frequency and higher power demands. Materials research and development will be needed to meet thermal management challenges for thermal interface materials, heat spreaders and external solutions. Knowledge of substrate materials properties is critical for modeling and simulation of electrical, thermal and reliability performance. The establishment of a materials database that makes data widely available will be very important.

Integrating Opto

Optoelectronics packaging brings together two realms of component packaging--the traditional electronics packaging with its associated issues and the integration of optical components into the optoelectronics package. The electronics packaging issues may be viewed as a special case of multichip packaging. I/O counts are typically lower than standard MCMs. The main issue is the high data rates and low signal levels of the converted optical signal with the integration of passive devices such as array waveguide gratings (AWG), filters, splitters, etc. Also, active devices including lasers, modulators, detectors, amplifiers, switches and attenuators are part of the OE package. An integral part of the optical-to-electrical and electrical-to-optical conversion is the high data rate, broadband electrical signals (FIGURE 1).

[FIGURE 1 OMITTED]

A better understanding of the materials properties and careful selection of assembly materials are necessary to successfully engineer OE packages. The OE package may contain substrates as diverse as silicon, gallium aluminum arsenide (AlGaAs), indium phosphide (InP), polymer and silicon germanium (SiGe) in various combinations in one package.

Beginning in 2000 and driven by mobile-phone applications, a shift occurred in multichip packaging where system-in-package (SiP) has become the fastest-growing area of packaging due to its associated system integration benefits. SiP enables OEMs to reduce size and weight while integrating more features and functions. This integration challenge may be best realized through cooperation between OEMs, their semiconductor device suppliers and microelectronic manufacturing service suppliers. Cellphone OEMs face shorter product lire cycles and have come to realize that designing new products is easier and more cost-effective when SiP are employed using available ICs versus inventing new ICs.

The definition of SiP has hot been well established across industry. The ITRS Assembly and Packaging Technical Working Group defines SiP as any combination of semiconductors, passives and interconnects integrated into a single package. This definition does not limit SiP to any one technology or integration approach. There are, however, a number of distinct types of SiP approaches for different market sectors. These include stacked-die, SMD mixed with bare the assemblies and build-up approaches.

An SiP can be manufactured using ceramic, leadframe, organic laminate or even tape-based substrates. The passive components can be either embedded as part of the substrate construction or attached via solder or epoxy to the substrate surface.

Die interconnect can be accomplished either by wire bonding, flip chip (solder or epoxy), and/or TAB to the SiP substrate or die-to-die. The final package configuration tan take the shape of a conventional ceramic style package, ball grid arrays, land grid arrays, and leadframe-based packages or custom modules. The resulting SiP uses die-to-die interconnection and high density substrate technologies to handle the higher wiring density requirements at the package level, thereby reducing the cost, wiring and I/O densities required at the motherboard and system level.

The SiP packaging concept is here to stay and can be considered as the fourth wave of packaging innovation. TABLE 3 provides a summary of future SiP technology requirements.

Wafer bumping is a key element to the successful implementation of flip-chip technology as noted by the ITRS. Eutectic Sn/Pb bumps on organic substrates represent the target against which potential solutions should be benchmarked.

Embedded Passives

Embedded passives on packages have been variously described to a) save package real estate, b) improve performance through shortened paths and c) reduce component and assembly costs. The alternate is discrete passives on package or implementation on chip. Embedded passives will be implemented only when there are competitive advantages in cost, performance or functionality as compared to discrete passives or on-chip passives. As the cost and size of discretes decrease, embedded passives will likely be implemented first in specific areas where discrete or on-chip solutions are hot suitable. While research in materials and manufacturing processes for embedded resistors, capacitors and inductors is proceeding, there is a need for integrated design tools.

Discrete resistors can achieve tight tolerance by sorting, and are extremely low cost and small sized. Embedded resistors are used not because of size or materials cost benefits. Instead, a designer may use embeddeds when discretes are insufficient to meet the needed performance due to parasitic inductance and capacitance. The most important issue for embedded resistors is their tolerance in performance-oriented applications.

The PCB could use a large number of terminating resistors. The savings from the piece parts and the assembly cost of large numbers of discretes may be sufficient tradeoff for additional costs associated with the embedded resistor layer and subsequent laser trimming. However, the materials resistance range, stability of sheet resistivity in long-term use and the temperature coefficient of resistivity still need improvement, particularly when used in package substrate applications.

If embedded resistors require an additional layer on the substrate, the additional layer cost would have to be amortized over the cost of all the resistor components. However, if they can be implemented over unused real estate on the substrate and require few additional process steps in substrate processing, the economic justification would be more compelling.

For RF applications, resistors in the range of 20 to 100[ohms] are used for load and termination. Discrete resistors may be sorted to get the precision required. Embedded resistors will need trimming to get the required precision. Those in the range of 100[ohms] to 250K[ohms] are used for biasing and circuit stability. The cost of a chip resistor and its assembly on a board is about one cent or less per resistor. This is the cost target for the trimmable, embedded on-package resistors.

Decoupling capacitors are needed as reservoirs of electrical charges to minimize switching noise in the electronics system. The rise/fan switching transition is very short in the IC, has a medium duration in the package and is longest on the printed circuit board. Therefore, designers want high-frequency decoupling capacitors on the IC, or very close to it, to minimize the series inductance and resistance, mid-frequency decoupling capacitors on the package, and low-frequency/high-capacitance decoupling capacitors on the PCB.

For RF applications, capacitors in the range of 1 to 100 pF with 10% tolerance are used for RF tuning circuits. Those in the range of 10 to 1000 pF with 10 to 15% tolerance are used for IF tuning circuits. Those in the range of 100 pF to 100 nF with 15 to 25% tolerance are used RF bypass applications. The embedded capacitors may achieve the 15% tolerance, and may be used for IF tuning, DC blocking and RF bypass.

For many applications in the 200+ pincount range, BGA packages will provide potential solutions (TABLE 4). Laminate-based BGAs will require underfills to reduce the shear stress load on the flip-chip interconnections for large dice, due to the large difference in the CTE between the silicon IC and the substrate. The area-array solder balls beneath the BGA package have the same pitch as that of the PTH or PTH pad on the substrate. To minimize the number of signal layers on the PCB, the signal leads underneath the BGA can be confined to the outer several rows.

Fine-pitch BGA/chip-scale packages (FBGA/CSP) provide a potential solution where low weight and small size are requirements. These packages are only slightly larger than the chip itself, and are available in a variety of configurations and materials combinations. The size may range from 4 to 21 mm. The 21-mm FBGA/CSP is for high lead-count applications. TABLE 5 shows examples of the maximum possible pincount for depopulated area array FBGMCSP solutions, by package size, array I/O pitch and number of rows. For these packages the solder-ball pitch is a fraction of the PTH on the PCB. Fanout wiring connections are required on the PCB to reach the PTH. To minimize fanout requirements, only a few of the outer rows of the area array connections are used. FBGA/CSPs at 0.5 mm pitch will put pressure on the PCB interconnect density for I/O escape to reach the inter-level vias or the PTH in the PCB. When the number of rows accessed is four or higher, a buildup layer on the PCB will be needed.

These packages provide potential advantages of higher performance, higher density and chip shrink transparency. For applications where FBGA/CSPs are redesigned to the minimum size possible each time the chip size is reduced, this redesign will drive a corresponding redesign of the PCB onto which the packages are assembled.

To accommodate FBGA/CSP solutions, the metal wiring on the top layer of the PCB needs to access the three outer rows. This means that the PCB should be capable of placing two 48 pro signal fines between the two adjacent solder ball pads at 0.4 mm pitch as indicated in Table 5. Buildup layers may be used to access the fourth and higher rows.

High current cost-performance and high-performance applications will need solder-bump flip-chips. TABLE 6 illustrates the key substrate features, expressed as a function of the flip-chip pad pitch, pad size and line width/spacing. When the outermost rows of chip pads are depopulated by 50%, one may place three lines between the pads at a two-pitch distance. For example, as of 2003, one may place three 32.1 [micro]m lines between the two pads at the 300 pm center-to-center distance. This gives four lines per two pitches, resulting in the equivalence of accessing two rows per fanout layer, or four rows per two fanout layers for the cost-performance applications. Similarly, one may place five 20.5 [micro]m lines between these two pads, and achieve the equivalence of accessing three rows per fanout layer as shown in Table 6.

All of the signal I/O pads and some of the voltage and ground pads are assumed to locate on a few of the outer rows, as shown in TABLE 7. Each of these outer row pads requires a fanout redistribution wire on the topside of the package substrate to reach a through via or PTH on the substrate.

Forecasted wiring geometries are not sufficiently dense to support moving on-chip wiring onto the substrate. A high Tg material is needed to meet the multiple cycles of high temperature Pb-free solder reflow during the chip-to-package assembly. It is important for the large chip to approach CTE matching between chip and package, and desirable between large packages and PCB. A low Dk material in the substrate will reduce the capacitance load to meet electrical performance needs. A low dielectric loss material is needed for the RF applications. And the low moisture absorption will improve the package reliability.

TABLE 1. Assembly and Packaging Challenges

DIFFICULT CHALLENGES    SUMMARY OF ISSUES

Improved organic         Tg compatible with Pb free solder
substrates               processing
                         Increased wireability at low cost
                         improved impedance control and
                         lower dielectric loss to support higher
                         frequency applications
                         Improved planarity and low warpage
                         at higher process temperatures
                         Low-moisture absorption
                         Low-cost embedded passives
                         Substrate cost is barrier to widespread
                         flip-chip adoption today
                         Increased vie density in substrate core
                         Alternative plating finish to improve
                         reliability

TABLE 2. Single-chip Packaging Technology Requirements

YEAR OF PRODUCTION      2003        2004        2005

                          PACKAGE PINCOUNT, MAX.

Low cost              112-408     122-500     134-550
Cost-performance      500-1452    500-1600    550-1760
High-performance        2400        3000        3400
Harsh                   450         500         550

YEAR OF PRODUCTION      2006        2007        2008

                          PACKAGE PINCOUNT, MAX.

Low cost              144-600     160-660     180-720
Cost-performance      550-1936    600-2140    600-2400
High-performance        3800        4000        4400
Harsh                   600         660         720

TABLE 3. System-in-Package Requirements

YEAR OF PRODUCTION               2003      2004      2005       2006

No. terminals-max., digital     800       1000      2000       2000
No. terminals-max., RF          100        150       200        200
Max. body size (L x W), mm       40         50        52         52
Min. terminal pitch, BGA          1.27       1.00      0.80       0.80
Min. terminal pitch, leadless     0.65       0.50      0.50       0.50
No. dice in SiP, max.             8         10        10         10
Embedded passives                Few        Yes       Yes        Yes

YEAR OF PRODUCTION               2007      2008      2009

No. terminals-max., digital     2000       2000       2000
No. terminals-max., RF           200        200        200
Max. body size (L x W), mm        52         52         52
Min. terminal pitch, BGA           0.80       0.80       0.65
Min. terminal pitch, leadless      0.50       0.50       0.5
No. dice in SiP, max.             10          8          8
Embedded passives                 Yes        Yes        Yes

TABLE 4. BGA Package Potential Solutions

YEAR OF PRODUCTION            2003    2004    2005    2006

Low cost and handheld          0.8     0.8    0.65    0.65
Cost-performance ball pitch    0.8     0.8    0.65    0.65
High-performance ball pitch    1       1      1       0.8
Harsh ball pitch               1       1.00   1.00    0.8

YEAR OF PRODUCTION             2007    2008    2009

Low cost and handheld          0.65    0.65    0.65
Cost-performance ball pitch    0.65    0.65    0.65
High-performance ball pitch    0.8     0.8     0.8
Harsh ball pitch               0.8     0.8     0.8

TABLE 5. Single-Chip Packages Potential Solutions

YEAR OF PRODUCTION                  2003        2004        2005

FBGA/CSP area array pitch (mm)      0.4         0.4         0.3
FBGA/CSP size (mm/side)             4-21        4-21        4-21
Low cost pincount                 112-408     122-500     134-550
Cost-performance pincount         500-1452    500-1600    550-1760
High-performance pincount           2400        3000        3400

YEAR OF PRODUCTION                  2006        2007        2008

FBGA/CSP area array pitch (mm)      0.3         0.2         0.2
FBGA/CSP size (mm/side)             4-21        4-21        4-21
Low cost pincount                 144-600     160-660     180-720
Cost-performance pincount         550-1936    600-2140    600-2400
High-performance pincount           3800        4000        4400

YEAR OF PRODUCTION                  2009

FBGA/CSP area array pitch (mm)      0.2
FBGA/CSP size (mm/side)             4-21
Low cost pincount                 180-720
Cost-performance pincount         600-2400
High-performance pincount           4400

TABLE 6. BGA and FBGA/CSP Package Potential PCB Solutions

YEAR OF PRODUCTION                     2003    2004    2005    2006

FBGA/CSP solder-ball pad pitch (mm)     0.4     0.4     0.3     0.3
Pad size ([micro]m)                   160     160     120     120
Line width ([micro]m)                  48      48      36      36
Line spacing ([micro]m)                48      48      36      36
No. rows accessed                       3       3       3       3

YEAR OF PRODUCTION                     2007    2008    2009

FBGA/CSP solder-ball pad pitch (mm)     0.2     0.2     0.2
Pad size ([micro]m)                    80      80      80
Line width ([micro]m)                  24      24      24
Line spacing ([micro]m)                24      24      24
No. rows accessed                       3       3       3

TABLE 7. Flip-Chip Substrate Top-side Fanout Potential Solutions

YEAR OF PRODUCTION                2003     2004     2005     2006

Flip-Chip pad pitch ([micro]m)    150      150      130      130
Pad size ([micro]m) *              75       75       65       65
Cost-performance                   12       12       12       12
High-performance                   17       17       17       17
Cost-performance (max.)            79       79       91       91
High-performance (max.)           112      112      129      129
Line width ([micro]m)              32.1     32.1     27.8     27.8
Line spacing ([micro]m)            32.1     32.1     27.9     27.9
Line width ([micro]m)              20.4     20.4     17.7     17.7
Line spacing ([micro]m)            20.5     20.5     17.7     17.7
Line width ([micro]m)              10.7     10.7      9.2      9.2
Line spacing ([micro]m)            10.7     10.7      9.2      9.3

YEAR OF PRODUCTION                2007     2008     2009

Flip-Chip pad pitch ([micro]m)    120      110      100
Pad size ([micro]m) *              60       55       50
Cost-performance                   12       12       12
High-performance                   17       17       17
Cost-performance (max.)            99      108      119
High-performance (max.)           140      153      169
Line width ([micro]m)              25.7     23.5     21.4
Line spacing ([micro]m)            25.7     23.6     21.4
Line width ([micro]m)              16.3     15       13.6
Line spacing ([micro]m)            16.4     15       13.6
Line width ([micro]m)               8.5      7.8      7.1
Line spacing ([micro]m)             8.6      7.9      7.1

* The pad size is assumed as 50% of pad pitch. It is usually
different at different fanout layers; e.g. from 30% to 60%.

JACK FISHER is founder of Interconnect Technology Consultants. He can be reached at 512-930-5666; [e-mail].