Silicon Perspective Corporation Corporation Wins AMD, TeraLogic, and VLSI Technology as New Customers.

SANTA CLARA, Calif.--(BUSINESS WIRE)--June 21, 1999--

First Encounter(TM) Integrated Into Design Flow 30-60 Days Before

Tapeout, Enabling Customers To Overcome Difficult Timing

Closure Issues!

Within two months after announcing their product, Silicon Perspective Corporation (SPC) successfully engaged three new high profile customers in their tapeout of critical projects.

SPC came in extremely late in the design cycles on production 1M+ gate 0.25 micron designs, and enabled all three customers to tapeout timing-correct implementations close to their original schedule using the First Encounter(TM) Front-End Physical Design Environment(TM).

The magnitude of the timing closure challenges faced by the three customers is demonstrated by the fact that they took the unprecedented step of considering another solution that late in the schedule. That all three became customers of SPC and met their tapeout schedules attests to the dramatic speed advantage of First Encounter's timing closure flow, the correlation with the customer's "golden" backend timing verification results, as well as the ease-of-integration into their existing Avant! (NASDAQ: AVNT - news), Cadence (NYSE: CDN - news), Mentor (NASDAQ: MENT - news), and Synopsys (NASDAQ: SNPS - news) flows.

AMD, TeraLogic, and VLSI Technology Get Their First Encounter

The three companies to complete tapeouts and join Trident Microsystems (NASDAQ: TRID) and the growing list of other Silicon Perspective customers are technology leaders AMD (NYSE: AMD), TeraLogic, and VLSI Technology (NASDAQ: VLSI), a subsidiary of Philips Semiconductors (NYSE: PHG).

AMD's Network Products Division had severe timing closure issues on several of the major modules in a 1.2M gate networking chip. Having experienced the long iteration times between logical and physical realms while chasing the timing closure issue with their present flow, it became obvious the project schedule was in jeopardy.

"The demo was impressive, but I didn't think it was possible for them to be able to ramp up in time to benefit the project," said John Szetela, NPD CAD Mgr. "Silicon Perspective came in and had the library and technology files converted within an hour, and the first place and route of the entire chip within that same afternoon after getting the netlist for the first time.

"To our surprise, the floorplan compared favorably to what we had attained after four months of work in our existing flow, and they did it without designer input and in less than one day! After having them duplicate the chip-level partitions that we had already been working with, we had to correlate the timing results from First Encounter with our own backend 'golden' router and extraction flow. The data were within about 10-12% for all nets, only they generated it in less than 20 minutes while it took us a week!"

Szetela continued, "Iteration times are extremely fast in First Encounter, and with our logic designers guiding the tool, we had timing closure on two of the three major modules within a week."

TeraLogic, a technology leader in the high definition TV (HDTV) market, had a similar timing issue with one module consisting of over 80,000 placeable cells and less than 30 days before scheduled tapeout. SPC came in parallel with the project and demonstrated its capabilities to the design team.

"The iteration times seemed too good to be true, until I saw it myself," said Sunil Malkani, Director of CAD at TeraLogic. "Because First Encounter achieved timing closure in this highly sensitive block within a week, we made the decision to use the company's technology in our final tapeout. SPC's new In-Place Optimization (IPO) capability was instrumental in gaining timing closure in such a short time. We're now implementing the full chip with First Encounter to further improve timing and reduce the die size through more optimum partitioning and pin assignment."

VLSI Technology had that same desire for more optimum partitioning and pin assignment on a 1.2M gate set-top box chip. With the high level of interconnectivity between blocks in this type of design, the partition and pin assignment information generated by the floorplanner can have a major impact on the physical implementation efficiency. First Encounter's unique Partition Magic(TM) option was able to generate optimal partitioning and pin assignments, resulting in a device with a much smaller die size compared with their existing flow.

"With First Encounter's unique ability to place and route a large design 'flat' while maintaining the logical hierarchy in the physical environment, Partition Magic automatically generated optimal hierarchical partitions and assigned the pins based upon this initial physical route," said Ram Gollapudi, Design Center Manager for VLSI's San Jose Tech Center. "The resulting die size savings of 10-15% is of major importance in a high-volume set-top box application."

About SPC:

Silicon Perspective Corp. is the pioneer and technology leader in Front-End Physical Design Environment tools and methodology for the DSM System-on-Chip (SoC) market. SPC's technology brings an unprecedented level of speed, accuracy, ease-of-use, and timing optimization to front-end physical design. Its integrated tool suite bridges the current gap between the logic and physical design teams, enabling a shorter time to timing-correct silicon and more efficient implementation.

The Company was founded in April 1996 by Ping Chao, President and CEO, and Wei-Jin Dai, VP of R&D, and is headquartered at 3211 Scott Blvd., Santa Clara, CA., 95054. Tel: [phone], Fax: [phone], Website: www.SiPerspective.com.

Note to Editors: First Encounter, Amoeba, Silicon Perspective Corporation, Front-End Physical Design Environment, Partition Magic, and FastTrack are trademarks of Silicon Perspective Corporation. All other trademarks are property of their respective owners.