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Silicon Perspective Corporation Announces Partition Magic.

SANTA CLARA, Calif.--(BUSINESS WIRE)--June 21, 1999--

New First Encounter(TM) option offers unique solution to

automated and optimized chip-level partitioning and pin

assignment for industry's largest designs

Driven by the needs of its customers working on some of the largest Deep Sub-Micron (DSM) chips in the industry, Silicon Perspective Corporation (SPC) today announced the immediate availability of a new option to its First Encounter Front-End Physical Design Environment.

Consistent with the company's philosophy, the product had not been announced until proving itself on production designs at several customers.

About Partition Magic(TM):

This patent-pending approach to partitioning huge designs to improve back-end efficiency or divide the task provides many unique solutions to problems that used to be done manually and with time-consuming trial-and-error.

Taking advantage of the fact that First Encounter has the ability to place and route designs "flat" that are in excess of 2M placeable cells (roughly 8M - 10M gates), essentially Partition Magic(TM) starts with a known placeable/routable solution. Then the user can go back to intelligently decide where to partition the design along logical boundaries while looking at an actual physical implementation.

Starting with a Verilog(R) netlist and timing files from synthesis such as Synopsys (NASDAQ: SNPS - news) Design Compiler(TM), Partition Magic(TM) automatically generates optimal partition shapes and helps predict the required area for each module. It then uses the Trial Route information to do an optimal and automatic pin assignment, with most pins between interconnected modules aligned directly across the channel from each other for most compact chip level routing and smaller die size. Each block is automatically cut out completely for independent back-end implementation, including netlist preparation, timing shell creation, and optimal pin assignment.

With First Encounter(TM), optimized final placement files are generated at both chip and block level for detailed routing by the customer's or ASIC vendor's existing router such as Avant!'s (NASDAQ: AVNT - news) Apollo(TM) or Cadence's (NYSE: CDN - news) Silicon Ensemble(TM).

Partition Magic(TM) provides an environment for seamless chip and block level floorplanning and constraint passing, as well as chip and block level timing closure. Each independently implemented block can be inserted back in at the top-level, and then flattened to do full chip timing analysis.

Other capabilities of First Encounter(TM) such as RC extraction, delay calculation, and timing analysis can be performed at the top-level with either an abstract or detailed view of the child partitions. Partition Magic(TM) also includes top-level IPO capability with intelligent buffer insertion based upon full knowledge of the physical implementation.

VLSI Technology had a need for such optimum partitioning and pin assignment on a recent 1.2M gate set-top box chip. With the high level of interconnectivity between blocks in this type of design, the partition and pin assignment information generated by the floorplanner can have a major impact on the physical implementation efficiency. First Encounter(TM)'s unique Partition Magic(TM) option was able to generate optimal partitioning and pin assignments, resulting in a device with a much smaller die size compared with their existing flow.

"With First Encounter(TM)'s unique ability to place and route a large design 'flat' while maintaining the logical hierarchy in the physical environment, Partition Magic(TM) automatically generated optimal hierarchical partitions and assigned the pins based upon this initial physical route," said Ram Gollapudi, Design Center Manager for VLSI's San Jose Tech Center. "The resulting die size savings of 10-15% is of major importance in a high-volume set-top box application."

Product Availability and Pricing:

Partition Magic(TM) is currently available and in production. Pricing for the option (single-job floating license) is $50,000 in the U.S.A. Existing customers of SPC will receive the option as a free upgrade. It is currently supported on UNIX platforms from Sun and HP.

About SPC:

Silicon Perspective Corp. is the pioneer and technology leader in Front-End Physical Design Environment(TM) tools and methodology for the DSM System-on-Chip (SoC) market. SPC's technology brings an unprecedented level of speed, accuracy, ease-of-use, and timing optimization to front-end physical design. It's integrated tool suite bridges the current gap between the logic and physical design teams, enabling shorter time-to-working-silicon and more efficient implementation.

The Company was founded in April 1996 by Ping Chao, President and CEO, and Wei-Jin Dai, VP of R&D, and is headquartered at 3211 Scott Blvd., Santa Clara, CA., 95054. Tel: 408/327-0900, Fax: 408/727-4450, Website: www.SiPerspective.com.

Note to Editors: First Encounter, Amoeba, Silicon Perspective Corporation, Front-End Physical Design Environment, Partition Magic and FastTrack are trademarks of Silicon Perspective Corporation. All other trademarks are property of their respective owners.
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Publication:Business Wire
Date:Jun 21, 1999
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