Silicon Magic Introduces DVine -- Industry's First Chip-Multi-Processor Architecture With Embedded DRAM for Consumer Electronics Products.

Business Editors, Techology Writers

SUNNYVALE, Calif.--(BUSINESS WIRE)--March 13, 2000

DVine Provides Substantial Time to Market, Performance, and Space

Benefits, Along with Programmability and Scalability of a True SOC

Development Platform

Silicon Magic Corp. today introduced DVine(tm), the semiconductor industry's first Chip-Multi-Processor (CMP) architecture that enables OEMs to implement system-on-chip (SOC) devices for next-generation consumer electronics products.

For OEMs adopting DVine in their products, the benefits include: higher performance and efficient space/area utilization through SOC integration; flexibility, scalability and programmability; greater design reusability and productivity; and faster time to market.

"OEMs developing digital consumer products face a tremendous challenge in designing SOC devices to meet aggressive market schedules," said Shubha Tuljapurkar, vice president and general manager of Silicon Magic's Audio Video Products business unit. "To leverage R & D dollars most effectively, OEMs need a common architecture foundation that can be used across a family of products to meet market demands for increasing functionality. Silicon Magic's DVine architecture enables OEMs with a highly scalable and programmable solution engineered from conception for audio/video signal processing, which is the core of next-generation consumer devices. OEMs using DVine can quickly implement required functionality while maintaining the flexibility to program their devices for new applications that evolve over time."

The DVine (DRAM Vector engine) architecture combines a modular hardware architecture with an integrated software development environment to enable rapid SOC-based product development. The basic architecture integrates multiple Computing Modules (CMs) with an appropriate amount of high-performance, embedded DRAM as dictated by the target application. Each identical CM combines both scalar and vector processors for optimal performance in media-centric processing applications such as camcorders, DVR (Digital Video Recorders) players, and information appliances.

Modular Architecture Eases Design and Product Migration

DVine's CMP architecture with embedded DRAM allows faster development cycles than traditional ASICs and greater reusability than designs assembled from discrete processor and memory devices. Based on Symmetrical Multi-Processor (SMP) architecture with Single Instruction Multiple Data (SIMD) extensions, this unique approach provides superior scalability over both monolithic RISC/CISC architectures and more specialized "media processor" architectures. OEMs can expand their product functionality and performance by simply adding CMs and embedded DRAM as necessary to their SOC designs.

The DVine architecture employs a shared-memory SMP programming model to support rapid software development and migration to successor products. Significant software engineering advantages are gained from this programming model, which is easy to understand and write, simple to debug, and readily extendible.

Application adaptability differentiates this architecture from other offerings on the market. Programmability coupled with the ability to scale the amount of processing power and embedded DRAM enables SOC implementations of the DVine architecture that can be easily adapted to different applications such as DVR, R-DVD and HDTV. The architecture is well suited for different Audio/Video compression algorithms such as JPEG, MPEG-1, MPEG-2, MPEG-4, Dolby Digital and AAC. Further, OEMs can offer product differentiation by programming DVine for new features for proprietary video post-processing and pre-processing enhancements.

The main features of the hardware architecture include:

High Performance Computing Modules

DVine is a scalable array of Computing Modules, each of which contains a Scalar RISC Processor (REX) and a Vector Processor (V16). Each CM also includes fast SRAM and registers that are shared between the Scalar Processor and the Vector Processor to allow data formatting, scalar processing, and vector processing to take place simultaneously.

Scalar RISC Processor (REX)

The REX processor is a high performance, 32-bit RISC processor with built-in instruction cache (I-Cache). The REX processor performs single issue, in-order instruction execution, has separate paths for instructions and data, and includes special registers for communication. The REX processor handles system supervision, data formatting, and task scheduling of the associated Vector Processor.

Vector Processor (V16)

The V16 processor is a nine-stage, 16-channel Single Instruction Multiple Data (SIMD) array of computing elements. The V16 processor is based on a dual-extension-unit architecture rather than multiplier/accumulator (MAC) architecture. This structure allows efficient motion estimation, but does not preclude MAC functions.

Each computing element processes one data sample in parallel with the other computing elements. The V16 processor is capable of very efficient, high throughput computation on vectors such as image, video, and audio data. This includes motion estimation, motion compression, DCT, quantization, filtering and scaling.

Low-Latency, High-Bandwidth Embedded DRAM

Embedded DRAM increases performance by eliminating the delays inherent whenever data must be transferred between devices in a traditional discrete processor and memory design. The DVine architecture contains embedded DRAM arranged as banks within modules. The standard configuration is 2 Mbytes: two modules, each of which contains two 1/2-Mbyte banks. The exact amount of embedded DRAM can be changed to meet the requirements of the application. Dividing the memory into banks provides large performance gains in a highly parallel architecture such as DVine.

Memory Interface Unit

The Memory Interface Unit (MIU) contains an Access Controller that has all of the circuitry needed to drive, address, and refresh the embedded DRAM. This allows the Scalar Processor to focus on the data setup and control functions for the Vector Processor. The MIU also has a Streaming Memory Processor that performs advanced data operations such as logical to scatter mode address conversion, data interpolation, and data sub-sampling. The MIU connects to the 128-bit Data Communications Channel (DCC) through the DCC Interface unit.

DCC and External Bus Interface Unit

Data and commands within DVine are carried on the 128-bit wide DCC, which is comprised of a multi-channel bus that can connect any CM to any MIU or to the External Bus Interface Unit.

The DCC and External Bus Interface Unit provide a high-bandwidth 64-bit bi-directional interface to DVine running at a speed of up to 54 MHz. The External Bus Interface is used to input and output all commands and data. A 256-byte FIFO buffers read/write operations, and also contains the configuration, general-purpose, and semaphore registers. The External Bus Interface can be connected to a system ASIC, other DVine devices or external Synchronous DRAM (SDRAM) with an optional SDRAM controller.

The CIO Bus provides eight bits of user-programmable Configurable I/O. It is connected to every CM within the DVine device.

DVine Integrated Software Development Environment

The DVine architecture has a complete, high-level GUI-based software development environment. User application programming is performed in C, reducing development time and costs. Integrated tools included in the development suite include an optimized C compiler, a debugger, a cycle-accurate simulator, and a performance profiler.

Silicon Magic has developed an extensive library of C-callable DSP functions that have been optimized for the DVine architecture. These ready-to-use functions can further reduce development time and effort. The DVine software development environment is available for both Unix and Windows platforms.

Performance Proven in Working Silicon

Silicon Magic has already proven the functionality and performance of DVine in prototype 0.25-micron silicon. Projected performance specifications in 0.18-micron silicon with a system clock rate of 200 MHz are:

Computing Module

         REX performance                   167 MIPS
         V16 Vector Processor              6.4 GOPS (16-bit Integer)
         Peak Memory Bandwidth             3.2 GBytes/sec
         Silicon Area                      6 mm(square) (incl. caches
                                              and Registers)
         Power                             0.3 mW/MHz
Memory Interface Unit

         Streaming Memory Processor
          Performance                      6.4 GOPS
         Peak Memory Bandwidth             3.2 GBytes/sec
         Silicon Area                      3 mm(square)
         Power                             9 mW/MHz

X-Bus Interface
         Performance                       432 MBytes/sec

Availability

OEMs interested in the DVine architecture can purchase the DVine Architecture Evaluation Platform for $ 18,500 each. This includes a PCI card with evaluation DVine silicon (6 CM and 4 MB of embedded DRAM) and evaluation DVine application software. Also included is a custom A/V breakout box for standard A/V connections.

A Windows 98 PC is the host platform.

DVine architecture licensing is a negotiable combination of IP license fees and royalties based on volume. Also available for licensing, if required, is the Silicon Magic DRAM Macro.

About Silicon Magic

Silicon Magic Corporation, headquartered in Sunnyvale, California, was founded in 1994 to be a semiconductor industry leader in the consumer electronics and information appliance markets. The company is known for its innovative high bandwidth DRAM memory products. Silicon Magic also provides system-on-a-chip (SOC) and application-specific standard products (ASSPs) with a highly integrated architecture utilizing the physical and electrical advantages of the Company's unique high bandwidth embedded DRAM macros. Silicon Magic tailors the design of these solutions to tackle the stringent requirements of emerging markets through the use of extensive design engineering and system-level integration expertise in the processor, storage, and memory domains. For more information, please contact Silicon Magic at 408/331-8000 or visit www.simagic.com.