Silicon Laboratories Introduces Industry's Lowest Jitter SONET/SDH Clock Multiplier IC; Si5320 is Latest Addition to Cesium Precision Clock IC Family.

Business Editors & High-Tech Writers

AUSTIN, Texas--(BUSINESS WIRE)--Nov. 5, 2001

Silicon Laboratories Inc. (Nasdaq:SLAB) today announced the Si5320 Cesium(tm) SONET/SDH precision clock multiplier integrated circuit (IC), the industry's first clock multiplier IC capable of generating the ultra low jitter reference clocks required in high-speed SONET/SDH optical port cards and transponder modules. The tiny 9 by 9 mm Si5320 is at least five times smaller than existing solutions based on clock generator modules or discretely implemented analog phase-locked loops (PLLs). In addition, the Si5320 uses Silicon Labs' patented DSPLL(tm) technology to achieve industry-leading jitter generation that is typically 0.25 ps (RMS) in OC-192 applications. This level of performance easily exceeds the strict jitter requirements for reference clocks in today's demanding OC-48, OC-192 and 10 GbE applications.

The Si5320 minimizes design complexity and manufacturing issues associated with low jitter clock synthesis circuits. The Si5320 generates standard SONET/SDH reference clocks centered at 19, 155 or 622 MHz from six different input clocks ranging from 19 to 622 MHz. For long haul applications, the Si5320 integrates all the necessary circuitry to translate between standard SONET/SDH reference clock frequencies and their equivalent 15/14 forward error correction (FEC) frequency. This replaces two PLL circuits with one Si5320 IC, saving significant amounts of board space, power and circuit complexity.

"With the Si5320, Silicon Labs' Cesium product line now serves the full range of clocking applications in SONET/SDH optical networking equipment. The Cesium products use our DSPLL technology to provide state-of-the-art clock generation in a single IC that meets or exceeds the performance of the best discrete or module based solutions, saving design time, board space, and power," said Jim Templeton, vice president and general manager of Silicon Labs' Optical Networking Division. "We are very pleased with the exceptional market acceptance of our Cesium products. Over 30 of the leading optical companies worldwide have designed in or are evaluating the Si5320."

Based on Silicon Labs' DSPLL technology, the Si5320 provides the ultra low jitter clock generation that previously required discrete analog PLLs based on expensive crystal based voltage controlled oscillators (VCXOs). With the patented DSPLL-based architecture, digital signal processing techniques are used to move sensitive analog parts of the PLL architecture into the digital domain, allowing the Si5320 to deliver industry-leading jitter performance in a single IC. This saves board space and simplifies board layout while improving clock jitter performance by eliminating the noise entry points found in discrete PLL implementations.

The Si5320 supports the growing need for clock cleaning in high-speed optical line cards and transponder modules by providing user selectable loop filter settings of either 200, 800 or 6,400 Hz. This narrow band PLL capability allows the user to match the level of jitter attenuation to the requirements of the application, an option unavailable in existing clock generation solutions.

Pricing and Availability

The Si5320 is priced at $59.87 in quantities of 1000. Samples and early production volumes are available now. An evaluation board, the Si5320-EVB, is also available.

Silicon Laboratories Inc.

Silicon Laboratories Inc. designs, manufactures, and markets proprietary high-performance mixed-signal integrated circuits (ICs) for the wireless, wireline and optical communications industries. Silicon Laboratories is an ISO9001-certified manufacturer and has applied for more than 100 patents on its mixed-signal technology. The company was incorporated in 1996 and is based in Austin, Texas. Silicon Laboratories' news releases and product information may be obtained at www.silabs.com.

Cautionary Language

This press release may contain forward-looking statements based on Silicon Laboratories' current expectations. These forward-looking statements involve risks and uncertainties. A number of important factors could cause actual results to differ materially from those in the forward-looking statements. Silicon Laboratories believes that it is important to communicate the company's future expectations to investors. However, there may be events in the future that Silicon Laboratories is not able to accurately predict or control. For a discussion of these and other factors which could impact Silicon Labs' financial results and cause actual results to differ materially from those in the forward-looking statements, please refer to Silicon Labs' recent filings with the SEC, particularly the Form 10-K filed January 22, 2001, the Form 10-Q filed April 24, 2001, the Form 10-Q/A filed July 24, 2001, and the Form 10-Q filed October 22, 2001.

Note to editors: Silicon Laboratories, Cesium and the Silicon Laboratories logo are trademarks of Silicon Laboratories Inc. All other product names noted herein may be trademarks of their respective holders.