Silicon Laboratories Expands Family of Low Jitter SONET/SDH Clock Multiplier ICs; Fully Integrated, High Performance Si5318 Ideal for 2.5 Gbps Line Cards.

AUSTIN, Texas -- Silicon Laboratories Inc. (Nasdaq:SLAB) today announced the Si5318, the newest addition to the company's family of SONET/SDH precision clock multiplier ICs, which are capable of generating the ultra low jitter reference clocks required in high-speed SONET/SDH line cards. Based on the company's DSPLL(R) technology, the Si5318 delivers jitter generation as low as 0.7 ps RMS, far lower than OC-48/STM-16 jitter specifications, while requiring no external components and less than one-fifth the board space of discrete solutions.

Unlike competing solutions based on hybrid combinations of analog circuitry, crystals or SAW-based oscillator elements, Silicon Laboratories' precision clock ICs are based on its patented DSPLL technology, which uses digital signal processing techniques to create a fully integrated phase-locked loop (PLL). The wide tuning range of the DSPLL enables one design to support a broad range of frequencies that would traditionally require multiple crystal or SAW-based PLLs. This frequency agility allows one Si5318 design to handle both SONET/SDH and forward error correction (FEC) rates, minimizing bill-of-material (BOM) complexity and saving R&D expense.

"The Si5318 is the smallest, most highly integrated jitter attenuating PLL IC designed for the OC-48/STM-16 market," said Brad Fluke, vice president and general manager of Silicon Laboratories. "Silicon Laboratories is committed to providing innovative timing solutions for the networking market and will continue to be a leader in performance and integration for precision clock applications."

Silicon Laboratories' DSPLL technology relies on a low phase noise, high frequency on-chip digitally-controlled oscillator (DCO) to produce a frequency agile, low jitter output clock with jitter performance rivaling that of discrete solutions. The low phase noise characteristic of the silicon-based DCO enables narrowband loop operation for applications requiring jitter attenuation. The Si5318 provides user-selectable loop filter bandwidths ranging from 800 Hz to 12800 kHz, allowing the user to easily match the level of jitter attenuation to the amount of clock cleaning required by the application, a feature not available with discrete PLL solutions.

Since the DSPLL integrates all PLL components into a single device, it provides greater immunity to system noise sources and simplifies layout. Competitive solutions built with discrete PLL components have multiple noise entry points, which require special layout precautions to protect sensitive analog nodes from board level noise that can increase clock jitter.

The Si5318 generates a single output clock in the 19 or 155 MHz range from a reference input ranging in frequency from 19 to 155 MHz. The Si5318 is packaged in a 9 x 9 mm CBGA.

Pricing and Availability

The Si5318 is priced at $32.00 in quantities of 1000. Samples are available now with volume production available in July 2005. An evaluation board, the Si5318-EVB, is also available for $350.

Silicon Laboratories Inc.

Silicon Laboratories Inc. is a leading designer of high-performance, analog-intensive, mixed-signal integrated circuits (ICs) for a broad range of applications. Silicon Laboratories' diverse portfolio of highly integrated, patented solutions is developed by a world-class engineering team with decades of cumulative expertise in cutting-edge mixed-signal design. The company has design, engineering, marketing, sales and applications offices throughout North America, Europe and Asia. For more information about Silicon Laboratories please visit www.silabs.com.

Cautionary Language

This press release may contain forward-looking statements based on Silicon Laboratories' current expectations. These forward-looking statements involve risks and uncertainties. A number of important factors could cause actual results to differ materially from those in the forward-looking statements. Silicon Laboratories believes that it is important to communicate the company's future expectations to investors. However, there may be events in the future that Silicon Laboratories is not able to accurately predict or control. For a discussion of these and other factors that could impact Silicon Laboratories' financial results and cause actual results to differ materially from those in the forward-looking statements, please refer to Silicon Laboratories' recent filings with the SEC, particularly the Form 10-K filed February 15, 2005.

Note to editors: Silicon Laboratories, DSPLL and the Silicon Laboratories logo are trademarks of Silicon Laboratories Inc. All other product names noted herein may be trademarks of their respective holders.