Silicon Design Systems Delivers ''Killer App'' Next-Generation Router to Tackle Nanometer Design Challenges.

SUNNYVALE, Calif. -- Revolutionary K-Route(TM) Placement-Independent Interconnect Synthesis Melds Routing and Optimization for Predictable Convergence and Best Quality of Results

Physical design tools company Silicon Design Systems, Inc. today announced its flagship product, K-Route -- a next-generation IC router with an automated flow, and fully automatic geometrical and electrical convergence. It leapfrogs traditional closure methodologies in efficiency and predictability to improve the bottom line of each physical design project. Unlike other solutions, K-Route's Interconnect Synthesis implementation is placement-independent because it uses its own powerful incremental placement engine, and easily can be plugged into any physical design flow. The company expects K-Route to revolutionize routing similar to the way Physical Synthesis impacted placement. Priced at U.S. $495k for a one-year license, K-Route is available now.

In contrast to traditional design methods that require preventive early over-design prior to detailed routing, to reduce post-routing optimization -- a costly approach in terms of area, power and performance -- K-Route replaces traditional post-placement flows with a new, far more efficient progressive design closure that uses intra-route optimization. Companies sensitive to area, power and performance no longer need to sacrifice predictability and time to market to improve result quality; K-Route is generating strong interest among companies evaluating its capabilities.

According to Nir Sever, Sr. Director, VLSI Design and Technology at Zoran Microelectronics, "Our company develops devices for consumer electronics applications with an aggressive die size target. The idea of concurrently optimizing our designs during the routing process, rather than afterwards, appeals to us as it can potentially allow us to achieve higher utilizations. K-Route holds great promise for us, and we are actively investigating its benefits. We have used SDS technology in the past to achieve substantial value in terms of die size and predictability."

Naveed Sherwani, President and CEO at Open Silicon, said, "Closure predictability and time to market are key elements for success in our competitive environment. We feel that K-Route's unique approach of progressively optimizing the design can bring great benefit to our time to market."

"One of the biggest challenges in our CMOS image sensor chip design is the floor-plan, which must take into account the embedded sensor array optics and the ISP," explained Eli Assoolin, CAD and Backend Manager at TransChip. "Due to the size and centrality of our imager array, we cannot afford to compromise on router quality which must accommodate the special shape of the digital logic. Therefore, we are evaluating the most promising state-of-the-art technologies such as Silicon Design Systems' K-Route, which shows potential in providing better results in terms of area timing and power consumption."

Improved Quality of Results

K-Route's physical closure helps ASSP, high-end ASIC and SoC chip designers achieve smaller, faster, lower-power chips, faster time to tape-out, and better design for manufacturing. By interleaving routing, analysis and repair during the entire convergence flow, K-Route eliminates the need for prevention margins, and improves the predictability and quality of results. Among K-Route's key differentiators are placement independency, a progressive optimization flow, fast and incremental analysis and optimization engines, a fine-grained concurrent architecture, dynamic list management, and super-signal(TM) modeling.

"Silicon Design Systems, as a design service firm, developed analysis and optimization tools for more than 10 years to serve our own internal needs," said Jacob Greidinger, Interim CEO and VP of R&D at Silicon Design Systems. "Two years ago, we decided to apply our expertise externally and began coding and integration of this brand new approach to interconnect synthesis. K-Route, the result of this 24 month concentrated effort, conquers traditional routing inefficiencies with dynamic new methodology that automates the entire process to achieve highest-quality results. We view it as a 'killer application' that takes the guesswork out of physical closure."

Novel Routing Drives Efficient Closure

K-Route's unique architecture, AFRA, which stands for "Adaptive Fine-grained Routing Architecture," is the key enabler for intra-route analysis and optimization. AFRA allows K-Route concurrently to perform fine-grained analysis and to optimize signal integrity, timing and noise issues during detailed routing. The specific optimization method to be applied is selected from among many potential solutions based on complex gain-effort analysis and the stage of convergence.

K-Route's unique database is based on a novel "super-signal" concept that treats buffers and inverters as part of the net, allowing experimentation and modification of the net topology. This unique modeling enables incremental global routing changes within detailed routing, including needed changes to buffers, inverters and cell sizing.

Concurrently with electrical and geometrical optimizations, K-Route applies Design for Manufacturing (DFM) improvements to better the manufacturability of the design. This intra-route approach eliminates the inefficiencies of post-routing DFM methods existing today, without sacrificing electrical design quality.

About Silicon Design Systems

Silicon Design Systems, Inc. is a privately held Electronic Design Automation (EDA) company headquartered in Sunnyvale, Calif. Delivering breakthrough progressive routing, its K-Route product uses an adaptive fine-grained routing architecture (AFRA) to provide superior quality of results. For more information about next-generation physical design tools and how to achieve the best quality of results -- smaller, faster, lower-power designs, and faster time to tape-out -- visit: www.SiliconDS.com.

Note to Editors:

Silicon Design Systems, the Silicon Design Systems logo and super-signal are trademarks of Silicon Design Systems.