Silerity addresses high-performance datapath design; PathBlazer automatically explores architectural trade-offs, optimizes placement.PASADENA, Calif.--(BUSINESS WIRE)--June 5, 1995--Silerity Inc., based here, today unveiled PathBlazer, a datapath synthesis tool that allows designers to explore all architectural trade-offs and optimize a design for sub-micron placement. PathBlazer, Silerity's first product entry, uses a unique synthesis approach called "Function-Level Optimization optimization Field of applied mathematics whose principles and methods are used to solve quantitative problems in disciplines including physics, biology, engineering, and economics. " to optimize designs at a higher level of granularity The degree of modularity of a system. More granularity implies more flexibility in customizing a system, because there are more, smaller increments (granules) from which to choose. than conventional "gate-level" optimization. As a result, PathBlazer can explore all architectural options for a complex datapath and optimize performance by considering placement. PathBlazer is based on a new synthesis paradigm called Function-Level Optimization. This approach allows PathBlazer to explore architectural trade-offs that would be lost ordinarily or·di·nar·i·ly adv. 1. As a general rule; usually: ordinarily home by six. 2. In the commonplace or usual manner: ordinarily dressed pedestrians on the street. at the gate level, maintain local optimization and operate at speeds up to 100 times faster than existing synthesis tools that operate at the Boolean level. Silerity has filed several patent applications related to this technology. Demonstrations of Silerity's PathBlazer will be shown continuously during the Design Automation Conference (DAC See D/A converter and discretionary access control. DAC - Digital to Analog Converter ) at the Moscone Convention Center in San Francisco San Francisco (săn frănsĭs`kō), city (1990 pop. 723,959), coextensive with San Francisco co., W Calif., on the tip of a peninsula between the Pacific Ocean and San Francisco Bay, which are connected by the strait known as the Golden June 12-14 in the Silerity Booth #2525 and the Viewlogic Booth #702. "To designers, logic synthesis The conversion of a high-level electronic circuit description into a list of logic gates and their interconnections, called the "netlist." Every logic synthesis program understands some subset of Verilog and VHDL. can often feel like mashing  This article or section contains .The purpose of Wikipedia is to present facts, not to teach subject matter. at gates with stone tools," says Dr. David Johannsen, a Silerity founder and its chief technical officer. "With PathBlazer, there's finally an alternative that understands architectural trade-offs and placement considerations." The Silerity Approach PathBlazer optimizes the entire datapath. It explores all implementation alternatives -- hundreds or thousands in a matter of seconds or minutes -- and optimizes timing based on cell placement. PathBlazer can automatically explore all architectural options for a complex datapath and optimize performance by considering placement. It operates at speeds up to 100 times faster than existing synthesis tools that operate at the Boolean level. Datapaths -- collections of arithmetic elements, buses, registers and multipliers, typically multi-bits wide -- usually account for about 80 percent of an Application Specific Integrated Circuit integrated circuit (IC), electronic circuit built on a semiconductor substrate, usually one of single-crystal silicon. The circuit, often called a chip, is packaged in a hermetically sealed case or a nonhermetic plastic capsule, with leads extending from it for (ASIC (Application Specific Integrated Circuit) Pronounced "a-sick." A chip that is custom designed for a specific application rather than a general-purpose chip such as a microprocessor. ) circuit area, says Dr. Johannsen. "Datapath design is typically one of the largest bottlenecks in the ASIC design process because this section usually determines how fast the entire chip will run." Optimizing the datapath involves considering different architectures for function implementation, data representation, pipelining or parallel versus serial operation. Performance optimization also involves defining where elements will be placed on the chip so interconnect (1) To attach one device to another. (2) A physical port (plug, socket) or wireless port (transmitter, receiver) used to attach one device to another. delays can be minimized. Existing logic synthesis tools have several drawbacks: they deal with one datapath element at a time; they are not fast enough to exhaustively explore all implementation alternatives; and they don't consider placement. As a result, designers can't optimize their datapaths using synthesis. Most resort to time-consuming hand drawn design. Conventional tools require a designer to devise his or her own optimization schemes, try them out one by one, then compare results manually. Each run can take hours or days to complete and placement is not considered. Available on UNIX-based platforms in volume shipments in Q41995, PathBlazer will be priced from $40,000. Silerity's synthesis products will be marketed, sold and supported through an Original Equipment Manufacturers (OEM (Original Equipment Manufacturer) The rebranding of equipment and selling it. The term initially referred to the company that made the products (the "original" manufacturer), but eventually became widely used to refer to the organization that buys the products and ) agreement with Viewlogic Systems Inc. of Marlboro, Mass. Silerity was founded in 1991 with the mission to develop a new approach to the design of high-speed ASICs, allowing designers to quickly explore architectural trade-offs and optimize for deep sub-micron design. -0- PathBlazer is a trademark of Silerity. Silerity acknowledges trademarks or registered trademarks of other organizations for their respective products and services. CONTACT: Nanette Collins 617-437-1822 nanette@nvc.com |
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