SiByte Mercurian Processors to Deliver Industry Leading Performance, Power Efficiency, and Integration for Internet Infrastructure Market.

Business Editors/High-Tech Writers

Microprocessor Forum

SANTA CLARA, Calif.--(BUSINESS WIRE)--Oct. 9, 2000

Multi-Processor System Design Delivers 800MHz-1GHz at 10-13

Watts; Includes Two SB-1 MIPS64(TM) CPUs, L2 Cache, DRAM Controller,

10/100/1000 Ethernet MACs, PCI, LDT 

SiByte, Inc., a leading communication IC start-up, will announce Mercurian(TM), a new generation of ultra fast, highly integrated multiprocessor solutions for networking and communications equipment, at the Microprocessor Forum in San Jose this week. SiByte Corporate Fellow, Jim Keller, will provide details on the first Mercurian processor, the SB-1250, at the conference on Tuesday, October 10th.

Innovative Processor Design for Next Generation Networks

Explosion in bandwidth requirements coupled with insatiable demand for sophisticated network features and services (e.g. VoIP, VPNs) are driving network equipment vendors to seek silicon solutions that: 1) can handle very high-speed network processing within a strict power threshold, and 2) are easily programmable to adjust to the constantly evolving networking landscape.

The Mercurian processor tightly integrates onto a single chip multiple 64-bit SB-1 CPU cores (www.sibyte.com/news.html ) with large cache memory and integrated I/O. The result is a Chip Multi-Processor (CMP) platform that offers very high raw packet processing performance at low power, and the large memory and I/O bandwidth required to manipulate and move network data with maximum efficiency and speed. Furthermore, since the processor leverages the standard MIPS64 instruction set, customers can take advantage of existing tools and software support, thereby minimizing their programming effort.

The key to Mercurian's unique architecture is its intelligent, high-performance MP design built around a fast, on-chip internal bus called the ZBbus(TM). The ZBbus, which runs at half the CPU core clock with a data width of 256 bits (one cache line), connects all the major blocks of the processor including the CPU cores, cache memory, and I/O. To ensure that a read always returns the latest data, the bus implements the standard MESI protocol to maintain complete data and I/O coherence. At 500 MHz, the ZBbus achieves peak bandwidth of up to 128 Gigabits/second.

"We are bringing our expertise in high-end CPU architecture and implementation to address the needs of network processing," said Dan Dobberpuhl, SiByte's president and CEO. "Mercurian is the first processor to deliver all four of the key requirements for next-generation networks: Very high performance, low power, high functional integration, and complete programmability. Now, equipment vendors have an ideal high-speed processing solution for both control plane functions such as exception processing and data plane tasks such as packet look-up and queuing."

SB-1250 Features and Performance

Key features of the SB-1250 include; 1) on-chip symmetric multiprocessing with two SiByte SB-1 CPUs (at 1GHz, each CPU delivers 2200 Dhrystone MIPS at approximately 2.5 watts or 880 Dhrystone MIPS/watt), 2) large cache memory system with on-chip L2 and memory controller, 3) high-speed network and standard I/O, and 4) a comprehensive system control and debug unit.

The two SB-1 CPUs on the SB-1250 are completely symmetric. Each processor works with the same physical address space and either processor can initiate an I/O operation or service interrupts. This provides a high degree of flexibility in how the CPUs are used for processing network data (for example, one CPU can handle control plane functions while another handles fast-path processing).

Unlike L2 caches in most systems, the 512K L2 cache on the SB-1250 is shared by both processors and all I/O DMA masters. The L2 sits in front of a very high-performance DRAM controller that supports up to 8GB in memory. In total, the memory system on the SB-1250 can support peak memory bandwidth of up to 50 Gigabits/second.

The processor includes three 10/100/1000 Ethernet MACs that support the MII (10/100) and GMII (1000) standard interfaces to connect to external PHY chips. For faster data rates or in cases where Ethernet protocol processing is not required, the MACs can be configured into either three 8-bit or two 16-bit packet FIFO interfaces. Clocked at up to 200MHz, each 16-bit FIFO interface can provide up to 3.2 Gigabits/second in each direction, enabling OC-48 data rates.

The SB-1250 comes with two standard I/O options: a 32-bit wide PCI bus running at 33/66 MHz and LDT. LDT (Lightning Data Transport), a high-speed I/O interface defined by AMD and a consortium of companies including networking equipment vendors, logically looks like PCI but leverages high speed point-to-point controlled LVDS signaling. The SB-1250, using 8 bit wide links at 400 MHz clock, double data rate, can support peak bandwidth of 6.4 Gb/sec in each direction or approximately 12 Gb/second full duplex.

As a System-on-Chip platform, the SB-1250 also includes system I/O with two serial interfaces, a simple bus for connecting boot FLASH and slow I/O, a serial configuration interface (SMBus), and PCMCIA support. Interfaces to on-chip debug features include bus trace and performance monitoring functions.

Targeted at Control and Data Plane

The SB-1250 is ideal for both control and data plane applications. It can be used as a high performance system controller/exception processor to handle higher-level processing tasks such as setting of QoS parameters, load balancing, and policy based connection routing. The SB-1250 also delivers exceptional fast path processing capabilities in the data plane. For example, when used for a typical IPv4 L3 routing application, the SB-1250 can process up to 10 million packets per second at 1GHz (5 million packets/sec/SB-1 core), well above the packet rates required to support OC-48.

"SiByte is providing a high-end roadmap for the MIPS architecture. They deliver a combination of raw CPU performance and memory and I/O integration that yields outstanding overall system-level performance in next-generation network applications," said John Wakerly, consulting professor at Stanford University.

In addition to enterprise LAN and WAN applications, the SB-1250 is also ideal for Metropolitan area Networks (MAN) and intelligent service provider edge devices including high-end switch/routers, multi-service access platforms, Web server switches and content caching/switching appliances.

Broad Tools and Software Support

As a MIPS64 processor, the SB-1250 is compatible with the broad range of development tools and systems software for the MIPS architecture, including compiler suites, debug tools, and RTOS packages. These include support for the GNU tool chain (compiler, assembler, and debugger), and NetBSD, Linux(R), and VxWorks(R) systems software platforms.

SiByte has partnerships with third party vendors to offer a comprehensive set of tools and software support for the Mercurian processors. Current partnerships include Wind River Systems for VxWorks support and Corelis for JTAG/debug support.

Availability

SiByte anticipates samples of the SB-1250 will be available starting in Q1'01, with volume production in mid-2001. Evaluation boards will be available in late Q1'01.

About the Company

SiByte, Inc. is a privately held fabless semiconductor company focused on the Internet infrastructure equipment market. Based in Santa Clara, Calif., SiByte can be reached at 408/845-6600 or http://www.sibyte.com.

Note to Editors: SiByte is registered trademark of SiByte, Inc. Mercurian and ZBbus are trademarks of SiByte, Inc. MIPS and MIPS64 are registered trademarks of MIPS Technologies, Inc. All other trademarks are the property of their respective companies.