Ser/Des Design Lays Foundation For Datacom Performance.

New information technology and networks are pushing the limits of system performance. Powerful microprocessors, multimedia applications, ballooning file sizes, and wire and optical-based I/O are all straining the capability of current data communications interfaces, resulting in the stifling of overall system performance and hottlenecking data transfers between devices and remote locations. This is creating a growing need for higher speed data communications transceivers to harvest the potential of these more powerful new technologies and next generation devices.

Why is transceiver speed so important? As component performance improves and requirements on data bandwidth increase, the interface that receives and transmits their data within the communicating pipeline must also improve in order to keep up. For example, within the near future, the new NAS RAID and SAN storage devices' internal data rates and host-to-device interface (bus) will be so fast that anything less than state-of-the-art data receiver/transmitter circuits will become the network's roadblock. If data communications throughput is stymied, it will cause sluggish overall network performance and require the building of larger buffers to act as data holding tanks before transfer to the datacom pathway. The result: twin problems of diminished system performance and added cost. But these conditions can be prevented with the implementation of improved high-speed transceiver design standards (See Fig).

With a high-speed state-of-the-art transceiver circuit design, the internal logic's data transfer throughput rate is increased, eliminating potential snarls between communicating devices. Faster data transfers over the datacom pathway also prevents data stream interruption from occurring. The increase in speed minimizes the risk of throughput lag that sometimes occurs in audio/visual file transfers. Transceiver architecture design improvements enhance overall system performance, improve data throughput rates between devices, and require smaller buffer sizes.

Outsourcing Your Transceiver Design

Key to improving data transmission and receiving performance is the PHY (Physical interface) architecture. developed by Tality Corp., a subsidiary of Cadence Design Systems. This PHY data communications component, known as SerDes, is responsible for high-speed serial communication across a medium, like wire or optical, extracting the data streams or clocking signals and conditioning them for transport. The PHY architecture is the key building block for SAN, LAN, WAN, and high-speed chip-to-chip communications.

To guard against premature obsolescence and to obtain maximum speed and performance benefits, this important component is customized for each application. It is not a cookie-cutter type design. Some level of customization is always required. The Serial/Deserializer (SerDes) transceiver architecture is also devised to allow for easy adoption in different applications, and scaling when multiple high-speed serial links are required on a single integrated circuit.

Ser/Des-Infrastructure For Now And The Future

Tality's new 2.5 Gigabit per second transceiver implementation is the latest power and speed bump for Cadence's Serial-Deserializer communications interface series, positioning it as the continuing standard for data throughput in WAN, LAN, SAN, and high-speed, chip-to-chip communications for the next several years.

Today, an I/O speed gap exists--data bandwidth off of the chip has not kept up with on-chip clock speeds. The SerDes transceiver closes that gap and lays the fundamental groundwork for the future by providing the infrastructure for manufacturers to continually make improvements to their products without the danger of an 10 log-jam. (See Table).

To use an analogy, it's like building a new railroad train with improvements that allow each car to load (receive) and unload (transfer) passengers more quickly. The older car's architecture is capable of embarking/disembarking x number of passengers/second--and it works fine when only a "few" ride. However, as the cars carry more and more passengers and larger numbers of passengers want to enter and exit at the same time, the whole system bogs down due to the time it takes for receiving and unloading the cargo (in this case, passengers. The new cars can transfer more passengers on and off (maybe they have multiple doors) per second, resulting in an improved passenger throughput rate that relieves "flow" congestion, and allows the passengers to go on their way more quickly, thus improving the performance of the entire system. The high-speed SerDes transceiver module is like the railroad car--only its cargo is not passengers but bits.

About The 2.5GB Serial/Deserializer Transceiver

Tality's Ser/Des 2.5GB transceiver is a follow-on to its 1.25GB transceiver. The 1.25GB transceiver meets IEEE 802.3z Gigabit Ethernet and ANSI X3.230-1994 Fibre Channel communication standards. The Ser/Des circuit's intended purpose is to support high-speed transmission of data streams. It can be adapted for different standards in the LAN/WAN space, either at the chip or Macro level. Multiple Ser/Des architecture supports concentrator and high-speed backplane applications. It is suitable for implementation in standard CMOS, providing cost and time-to-market benefits.

The PHY design itself is in great demand because it is suitable for many applications. The advantage of this design is that it is a proven architecture having been successfully implemented in a number of earlier technologies, including slower speed 1.06/1.25GHz devices utilizing 0.25m m (micron) and 0.35m m CMOS and 0.8m m BiCMOS processes. This same architecture supports the newer 2.5GHz SerDes operation implemented in 1.8m m and 0.15m m processes for various standards.

The 2.5GB Ser/Des Transceiver provides higher speed performance at a lower implementation cost; it is also more customization "friendly" than previous versions. The transceiver's functionality, speed, and field-tested reliability make it ideal for use as an interface in applications such as high-speed backplane, Fibre Channel, Gigabit Ethernet, 10 Gigabit, and Infiniband communication.

Key design features of the 1.25/2.5GB Ser/Des include:

* 1 TX and 1 RX

* TX: 20:1 serialization/driver

* RX: 1:20 deserialization/sync detection/clock recovery

* COMMON: PLL/clock distribution/bias generation shared amongst multiple Ser/Des circuits

* CLKBUFF: clock buffer driving clocks from COMMON to RX/TX

The SerDes compatibility with industry-wide IEEE and ANSI design standards means it is simple and cost-effective for system and component manufacturers and their customers alike to integrate into new and existing products.

Cadence Design Systems originally developed and introduced its SerDes transceiver circuit series in 1998. The new, higher speed SerDes architecture provides the bandwidth capacity (2.5GB) to ensure that the high-speed transceiver interface is capable of providing the performance power to handle the data RX/TX needs of WAN, LAN, SAN and high-speed chip-to-chip communications for next generation networks and systems.

Ronald S. Gyurcsik, Ph.D. is the group director in the RTP Analog/Mixed-Signal Design Center at Tality Corp. (Cary, NC).