Sequence Design's Dr. Rob Mathews Joins High-Powered ISQED Statistical Design Panel Tuesday, March 19.Sequence Design:
WHO: Dr. Rob Mathews, Sequence Design VP of Extraction Products.
WHAT: ISQED ISQED International Symposium on Quality Electronic Design (IEEE) Panel: "Statistical Design - Solutions Searching for Problems?" Other panelists represent Cadence cadence, in music, the ending of a phrase or composition. In singing the voice may be raised or lowered, or the singer may execute elaborate variations within the key. , Extreme DA, Solido, Synopsys, TSMC TSMC Taiwan Semiconductor Manufacturing Company, Ltd
TSMC Taiwan Semiconductor Manufacturing Corporation
TSMC Traffic Systems Management Center
TSMC Toll Station Management Controller
TSMC Transportation Supply Maintenance Command
TSMC Technical Services Manager Code , Xoomsys, and the moderator is Mike Santarini.
WHEN: Wednesday, March 19, Noon
WHERE: Donner Room, ISQED 2008, Doubletree Hotel, San Jose San Jose, city, United States
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WHY: The panel will discuss statistical design as the salvation for design variability issues in sub-130nm designs. Although progress has been made, it has yet to be widely used. It is needed at the front-end of the process, but the information to support it is hard to get. Panelists will debate the viability of this approach and offer practical methods to employ statistical design effectively today.
BACKGROUND: Dr. Mathews advocates using Statistically Accurate Corners as an alternative to Statistical Static Timing Analysis Conventional static timing analysis (STA) has been a stock analysis algorithm for the design of digital circuits over the last 30 years. However, in recent years the increased variation in semiconductor devices and interconnect has introduced a number of issues that cannot be handled by (SSTA SSTA Saskatchewan School Trustees' Association
SSTA Scottish Secondary Teachers' Association (Scotland)
SSTA Sea Surface Temperature Anomaly
SSTA Statistical Static Timing Analysis
SSTA Security Seal Testing Authority ) in a recent article published by SOCcentral: http://www.soccentral.com/results.asp?entryID=24630.
Sequence Design accelerates the ability of SoC designers to bring high-performance, power-aware ICs quickly to market. Sequence Design-For-Power solutions give customers the competitive advantage necessary to excel in aggressive technology markets. For more information: www.sequencedesign.com.
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