Sequence DAC Demo Lineup and Signup; Power, Signal Integrity, Nanoscale Design Featured Attractions.

Business Editors/High-Tech Writers

Design Automation Conference 2002

SANTA CLARA, Calif.--(BUSINESS WIRE)--May 30, 2002

Sequence Design announces open registration on its Web site www.sequencedesign.com/dac2002.html for DAC demos June 10-13 in New Orleans.

The sessions will cover a variety of topics ranging from an overview of the company's NanoCool(TM) flow for design at 100 nanometers and below, to hands-on test drives of power analysis and optimization tools. Short program descriptions follow, but for complete demo information refer to the above link.

Low Voltage/Low Power Design Tools and Methodology

Describes a complete, working flow for sub-100nm, low-voltage/low-power design addressing crosstalk, voltage drop, leakage power, and clock optimization.

Full-Chip Low Power SoC Design, Analysis and Optimization

Of particular interest for low-power SoC, communications, wireless, and consumer designers, covers power optimization at the RTL level without simulation, using ALF to quickly construct highly accurate power models, and integration of the latest Sequence power products into existing flows.

High-Performance RF/Analog Design: Interactive RLC Extraction Solution

Highly accurate RLC extraction with Columbus(R)-RF sets the standard for RF, optical networking, instrumentation, and other high-performance circuits operating at frequencies of 1GHz - 40GHz. Demo describes the tool's tight integration with the Cadence Analog Design Environment, and a new Calibre interface.

ASIC/COT Standard Cell Design: Standard-Cell Extraction within Physical Studio(TM)

A key component of the PhysicalStudio product family, Columbus-Turbo quickly extracts routed designs above 1 million gates, on one or more CPUs, while retaining industry-leading accuracy.

Full-Custom Design: Flexible RLC Extraction Solution

Describes the use of Columbus-Gold RLC extraction together with leading LVS/DRC tools to avoid chip failures in full-custom digital and mixed signal designs. Columbus-Gold provides net-by-net extraction to obtain accurate R, C and L interconnect parasitics and good simulation-to-silicon correlation, even for large, high-speed custom designs.

Physical Design Closure for Sub-180nm Designs

Seamlessly interoperable with industry-standard routing tools, PhysicalStudio predicts and corrects chip timing, signal integrity, clock and power issues concurrently, before and after routing. An unprecedented feature set includes: hierarchical timing analysis and optimization; signal integrity analysis and optimization; unified pre-route avoidance and post-route correction; concurrent optimization for timing, signal integrity, power and clock.

Physical Analysis for Timing, Signal Integrity and Voltage Drop

Combining concurrent analysis of timing, crosstalk delay, crosstalk glitch and voltage drop in one tool, ShowTime(TM) lets designers eliminate multiple tools and achieve fast, accurate signoff -- as much as 10 times faster than existing static analyzers with better accuracy and closer correlation to SPICE.

About Sequence

Sequence Design, Inc., the SoC Design Closure Company(SM), enables system-on-chip designers to bring higher-performance and lower-power integrated circuits quickly to tape out. Sequence's physical design software and solutions give its more than 100 customers the competitive advantage they need to excel in aggressive technology markets, despite demanding complexity and time-to-market issues of sub-180 nanometer designs.

Sequence has worldwide development and field service operations. The company was formed through the merger of Sente, Inc., Sapphire Design Automation, Inc. and Frequency Technology. Sequence is privately held. Sequence is a member of Cadence Design Systems' Connections(TM) and Mentor Graphics' Open Door(TM) partnership programs. Additional information can be found at sequencedesign.com

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