Sequence Announces First 3-D RLC Extraction Solution for RF Designs; Fills Void in Design Flow for RF and Custom High-Speed Digital Designs.

Business Editors/High-Tech Writers

SANTA CLARA, Calif.--(BUSINESS WIRE)--May 30, 2000

Sequence Design Inc., the leading supplier of optimal design closure solutions has released Columbus-RF, the industry's first integrated 3-dimensional RLC interconnect extraction solution specifically tailored for RF, analog and custom high-speed digital integrated circuit (IC) designs.

With the high frequencies found in today's radio-frequency (RF) and high-speed digital designs, interconnect parasitic effects, including inductance, are a critical performance determinant and cannot safely be ignored.

Columbus-RF brings powerful new innovations to RF designs, including the industry's most accurate resistance-capacitance (RC) modeling, the ability to model inductance ("L") in RF circuits, and tight, on-line integration with Cadence Design Systems Inc.'s Analog Artist environment and Diva physical verification tools, the de facto industry standard design flow for RF, analog and custom high-speed digital designs.

"Interconnect is a critical contributor to RF and other high-speed chip performance, and must be modeled accurately -- including inductance," said Vic Kulkarni, senior vice president of marketing and product strategy at Sequence. "Designers will now be able to more accurately analyze their designs with full interconnect effects, and understand the effects of interconnect inductance on high frequency circuits during the design phase. This capability will allow RF designers to reduce risk and uncertainty in their high performance designs."

Columbus-RF leverages Sequence's patented Exact Topological Decomposition architecture, which accounts correctly for how a target net interacts with all other nets and not just with its nearest neighbors. This approach is central to Columbus-RF's high accuracy and will help designers avoid costly chip turns caused by errors in predicting circuit performance based on incorrect estimates of interconnect behavior,

3D Extraction for Interactive Design Styles

RF and custom high-speed digital designers generally follow a much more interactive design and physical verification style than traditional ASIC designers. These designers benefit from Columbus-RF's on-line integration with Cadence's Analog Artist / Diva design flow. The integration provides the interactivity consistent with the requirements of this design approach, enabling designers to add 3D RLC extraction to their design flows without impact to their productivity or design methodology.

About Sequence

Sequence Design Inc. is the premier provider of timing and power optimization for design closure in system-on-chip integrated circuits. Sequence's chip design software and services enable engineering teams to develop superior products quickly, in order to achieve competitive advantage in high-growth technology markets. Customers include Broadcom, Ericsson, Juniper Networks, LSI Logic, Nokia, Nortel Networks, MMC Networks, Sony, Sun Microsystems, Texas Instruments, Toshiba and Vitesse Semiconductor.

Sequence is based in Santa Clara, California with worldwide development and field service operations. The company was formed through the merger of Sente, Inc and Frequency Technology. The company is privately held; investors include IVP, Menlo Ventures, Alpine Technology Ventures, Intel, Sumitomo Corporation, and LSI Logic.

Sequence is a member of Cadence Design Systems' (NYSE:CDN), Mentor Graphics' (Nasdaq:MENT) and Synopsys' (Nasdaq:SNPS) partnership programs. Please contact Sequence at Technology Station, 469 El Camino Real, Suite 202, Santa Clara, Calif. 95050. Phone: [phone]. Or visit our web site at www.sequencedesign.com.

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