Sapphire Introduces Noise And Power Optimized Clock-Tree Synthesis Tool For SoC Design.

Business Editors/High-Tech Writers

SANTA CLARA, Calif.--(BUSINESS WIRE)--Nov. 6, 2000

ClockIT(TM) Produces Balanced Delay-trees, Uses Real Skew 

for Final Path Optimization

Sapphire Design Automation (Sapphire), an EDA company offering ElectricallyCORRECT(TM) design closure software, announced today the release of ClockIT(TM), a clock-tree synthesis tool for building clocks optimized for timing, noise, power and silicon area.

ClockIT reduces noise effects and power consumption in an electronic design. This is important because the clock signal is a significant contributor and injector of noise in an electronic design and may consume up to 10% of the total on-chip power. ClockIT produces designs with minimum skew and insertion delay 10x faster than traditional methods.

"ClockIT is unique because it works in existing flows," noted, Dhiraj Sogani, Director of Marketing at Sapphire Design Automation. "We believe that other tools cannot match our results, especially when you consider ClockIT handles noise and power constraints as part of its clock generation process."

ClockIt produces an optimized placed file for routing using placement input and clock constraints. A typical run of 10,000 sequential elements takes approximately four minutes on a Sun Ultra 10 machine.

What's Unique

ClockIT supports custom macros

In SoC design, pre-defined macros are used more because of reuse. ClockIT generates the correct skew and insertion delay for these macros by accepting their constraints.

ClockIT uses the right number of buffers, the right sizes and real skew

Right sizing the buffers reduces the power consumed by the clock signal. ClockIT propagates the actual tree and then does path and combinatorial logic optimizations using the real skew and insertion delay. In this way, clock convergence iterations are eliminated.

Design Tool and Flow Compatibility

ClockIT's synthesis is compatible with Cadence Design Systems (NYSE:CDN) and Avant! (Nasdaq:AVNT) physical design flows. It accepts placement files and standard parasitic formats such as DSPF (coupled) and SPEF. ClockIT can use the analysis from Sapphire's FormIT(TM), a design tool that takes gate-level netlists and forms them into a placed cell netlist format for routing to improve timing. Sapphire's NoiseIT(TM) tool can also be used to perform noise analysis and eliminate noise-generated delay and glitch due to the clock signal.

Price and Availability

ClockIT is available now. It runs under UNIX operating systems on Sun workstations at a unit cost of $100,000 (USD).

About Sapphire

Sapphire Design Automation addresses the emerging EDA market segment faced with the design closure issues of timing, power, noise and yield. Sapphire has developed an innovative approach to solving the timing, power, and signal integrity problems associated with deep submicron semiconductor technology. The Company offers software that dramatically improves design productivity and produces superior quality results for interconnect-dominated ASIC and SoC designs. The tools operate during placement to avoid problems and after routing for problem correction. Sapphire's brings an ElectricallyCORRECT physical design solution up front in the deep submicron design flow to shorten design cycle time and increase overall chip performance. For more information, visit www.sdai.com.

Contact information

Sapphire Design Automation, 2310 Walsh Avenue, Santa Clara, CA, USA 95051 408/970-0110, FAX: [phone], Kevin Walsh, [e-mail]

Acronyms

DSPF: Detailed Standard Parasitic Format EDA: Electronic Design Automation SoC: Systems-on-Chip SPEF: Standard Parasitic Extended Format

Note to Editors: FormIT, NoiseIT, ClockIT and ElectricallyCORRECT are trademarks of Sapphire Design Automation. All other trademarks are the property of their respective owners.