STMicroelectronics Adopts AXYS Design's MaxCore Product for Advanced DSP Processor Development.Business Editors/High Tech Writers PALO ALTO, Calif.--(BUSINESS WIRE)--July 16, 2001 AXYS Design's Tool Gives STMicroelectronics and its Customers Faster Access to Cycle-Accurate Processor Models and Tools for Embedded Software Development AXYS Design Automation, Inc., today announced that STMicroelectronics has adopted AXYS Design's MaxCore(TM) processor modeling and tool generation environment for use in their Telecommunication & Peripherals/Automotive Group. MaxCore will be used for architecture exploration and for the development of fast, cycle-accurate models for STMicroelectronics' leading ST100 family of DSP (1) (Digital Signal Processor) A special-purpose CPU used for digital signal processing applications (see definition #2 below). It provides ultra-fast instruction sequences, such as shift and add, and multiply and add, which are commonly used in math-intensive cores. "After evaluating a number of options for processor modeling, we chose MaxCore because of its unique model and tools generation capabilities," said Jean-Claude Michalina, general manager of STMicroelectronics' DSP & Micro Division. "The models and tools generated from MaxCore will help in the exploration of different microarchitectures, accelerate the proliferation of our DSP architecture and effectively support the development of embedded software and complex SoCs based on the ST100 architecture." Under the multi-year agreement, AXYS Design provides the MaxCore processor modeling environment to STMicroelectronics' ST100 DSP core design team. This design group will use the tool to create fast instruction-accurate and cycle-accurate simulation models of new processor cores in the ST100 family of high performance DSP cores. MaxCore can also automatically generate related embedded software development tools including disassemblers, assemblers and multiple integration packages from a formal processor description in the C-like LISA The first personal computer to include integrated software and use a graphical interface. Modeled after the Xerox Star and introduced in 1983 by Apple, it was ahead of its time, but never caught on due to its $10,000 price and slow speed. language. "As one of the leaders in the semiconductor industry, STMicroelectronics has recognized the need for fast and accurate processor and SoC models to enable the collaborative development of complex SoCs and the embedded software needed to effectively deploy these chips," said Vojin Zivojnovic, president and CEO (1) (Chief Executive Officer) The highest individual in command of an organization. Typically the president of the company, the CEO reports to the Chairman of the Board. of AXYS Design. "We are extremely pleased that STMicroelectronics selected MaxCore for the development of new complex processor architectures and to aid the proliferation of their IP to internal and external customers." About ST100 STMicroelectronics' innovative ST100 DSP processor core architecture has been conceived specifically for embedded applications in custom system-on-chip products for demanding markets like cellular phones, hard disk drives, engine management units, telecommunication systems and advanced multimedia products. A completely new design, the ST100 architecture combines in a single core the advantages of a 16-bit instruction word for code compactness, a 32-bit instruction word for MCU (1) (MicroController Unit) A computer on a single chip. See microcontroller. (2) (Multipoint Control Unit) A device that is used to moderate a videoconference of three or more end points (users at computers or groups of users performance and a 128-bit SLIW instruction word for high DSP performance. About MaxCore(TM) MaxCore(TM) automatically generates fast cycle-accurate processor models and software development tools from an architectural description in the C-like LISA language. The toolset supports a broad range of processor architectures including DSP, RISC RISC in full Reduced Instruction Set Computing Computer architecture that uses a limited number of instructions. RISC became popular in microprocessors in the 1980s. and VLIW (Very Long Instruction Word) A CPU architecture that reads a group of instructions and executes them at the same time. For example, the group (word) might contain four instructions, and the compiler ensures that those four instructions are not dependent on each and also generates assembler, disassembler Software that converts machine language back into assembly language. Since there is no way to easily determine the human thinking behind the logic of the instructions, the resulting assembly language routines and variables are named and numbered generically (A001, A002, etc.). and various integration packages automatically from the same description. The resulting tools and models can be integrated into leading third party tools and with AXYS Design's MaxSim(TM) and MaxLib(TM) products for simulation of complete SoCs. About AXYS Design Automation, Inc. AXYS Design Automation, Inc. is a provider of fast, accurate, and integrated processor and SoC C/C++ modeling and simulation solutions for the development of high-software content System-on-Chip (SoC) devices. The MaxSim(TM) environment enables fast, cycle-accurate, synchronous simulation of complex SoC designs incorporating multiple processor cores. MaxCore(TM) automatically generates cycle-accurate processor models and software development tools from an architectural description in the C-like LISA language. The use of AXYS Design's solutions in the pre-silicon phase substantially shortens the SoC design cycle by enabling early system integration and embedded software development, thus reducing NRE cost and time to market. AXYS Design's growing MaxLib(TM) model library includes processors from Conexant Systems (Nasdaq: CNXT), DSP Group (Nasdaq: DSPG DSPG Defense Special Projects Group ), Infineon Technologies (NYSE NYSE See: New York Stock Exchange : IFX, FSE FSE 1. feline spongiform encephalopathy. 2. focal symmetrical encephalomalacia. : IFX) and LSI Logic (NYSE: LSI). AXYS Design also offers cycle-callable/cycle-accurate models of the ARM (LSE LSE - Language Sensitive Editor : ARM, Nasdaq: ARMHY) ARM 7 and ARM 9 architectures and MIPS' MIPS (Million Instructions Per Second) The execution speed of a computer. For example, .5 MIPS is 500,000 instructions per second; 100 MIPS is a hundred million instructions per second. 32 and MIPS64 cores. For more information, visit the AXYS Design web site at www.AXYSdesign.com. MaxSim(TM), MaxCore(TM), MaxLib(TM) and AXYS are trademarks of AXYS Design Automation, Inc. All other trademarks are the property of their respective owners. |
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