STMicroelectronics Achieves Design Success With Sierra's Breakthrough Chip Assembly Solution; Enables Tapeout of a 90nm 20M Gates Chip With 5 Modes and 4 Corners in Less Than 4 Months.

SANTA CLARA, Calif. -- Sierra Design Automation, Inc., the technology leader in high-performance IC implementation solutions, today announced that STMicroelectronics, a leading supplier of semiconductors, has used the recently introduced version of Sierra Pinnacle(TM) product suite showcasing Advanced Chip Assembly to tapeout an advanced 90nm design. The company also announced that the product is in production and is actively being used at multiple customer sites.

"We used Sierra Pinnacle to tape out the most advanced and deeply integrated Set Top Box chip -- 20M gates, 90nm, 500MHz, 5 modes and 4 corners in less than 4 months," said Paul Gouldthorpe, ISS Division R&D Manager, Home Entertainment Group, STMicroelectronics. "We are very impressed with Sierra's new Chip Assembly and Top Level Optimization capabilities that remove the inaccuracies and inefficiencies caused by physical partitioning of designs. After implementing the blocks in Pinnacle, we were able to read in all the partitions without any timing or physical abstractions and optimize the top level with a flat and seamless view of the whole chip. Sierra's analysis and optimization engines simultaneously optimized the design for multiple modes and corners while addressing advanced requirements such as OCV and NBTI. Sierra Pinnacle is the only solution in the market that comprehensively solves the chip assembly challenge and combines the benefits of the traditional hierarchical and flat flows."

Sierra Pinnacle's Chip Assembly solution establishes a new paradigm that combines the strengths of the conventional hierarchical and flat design flows. It delivers the high capacity, runtime, and memory benefits of a hierarchical flow without sacrificing the high quality of results of flat flows. Technology highlights include:

--Infrastructure Enhancements -- Pinnacle provides a high capacity data model that can represent arbitrary levels of logical and physical hierarchy. The data model allows a "flat" view of the entire chip for accurate analysis and optimization while fully preserving the block-level design interfaces. The user is now given the freedom to choose which blocks to abstract and which not depending upon the top-level paths and the level of accuracy needed. For example, a block that is cloned heavily may need to be abstracted while a block that is not cloned can remain un-abstracted thereby giving greater accuracy to chip-level timing measurements.

--Full Chip STA Engine -- The signoff quality advanced timing engine native to the kernel seamlessly handles various nanometer effects such as modes/corners, complex clocking, case analysis, and other sign-off timing features with compact memory usage and fast runtimes. Incremental analysis infrastructure (extraction, delay calculation and STA) also enables rapid "what-if" queries for comprehensive analysis.

--Chip Level CTS -- Pinnacle provides a flexible clock tree infrastructure that enables full top-down or bottom-up or some hybrid of the two. The CTS engine is tightly integrated with the full-chip STA engine and thus eliminates the need to manually analyze the clock trees for the various nanometer effects. The engine is also cognizant of the block level interfaces resulting in a higher quality clocktree with less number of buffers.

--Chip Level optimization -- The optimization engines have been enhanced to take advantage of the "flat" view of the design. Because of the "flat" view of the design. The optimization algorithms seamlessly optimize the top-level as well as the block-level logic. In addition, the optimization engines can review pin assignment decisions incrementally and adjust them to obtain even better performance. Since block-level boundaries are maintained at every stage of the flow, the changes made to the blocks at the chip assembly stage are directly updating the block-level implementations.

"Our customers have told us that at 90nm, 65nm, and below, they are being adversely affected by the lack of variability aware chip assembly capabilities which often leads to chip failure, reduced yield, missed schedule and lost performance," said Pravin Madhani, President and CEO of Sierra. "There is currently no recourse for bad pin assignments, incorrect block budgets, abstractions, and lack of variability aware analysis and optimization engines. Unlike current solutions in the market which forces customers to tradeoff performance for capacity and runtime, Sierra's Pinnacle Chip Assembly empowers designers to get the best quality of results in the shortest times for multi-million gate designs."

About Sierra Design Automation and Pinnacle

Sierra Design Automation is a privately funded EDA company founded in January 2003. The Company's world-class EDA team is focused on providing semiconductor designers with innovative IC implementation solutions that comprehensively address the performance, capacity, time-to-market, and variability challenges occurring at the 90nm and 65nm process nodes. Variability includes process variations, lithography variations, manufacturing variations, and multiple design operation modes. Pinnacle, Sierra's flagship product suite, provides "The Fastest and the Best Design for Variability Solution for the Biggest Chips." Built on revolutionary architecture and with a signoff quality timer native to the kernel, Pinnacle delivers the best performance in the shortest possible time. Pinnacle's Adaptive variability engine analyzes and optimizes for DFV throughout the flow. Pinnacle's open architecture and ultra-compact database handle extremely large capacities and seamlessly plug into existing design flows. For further information visit: www.sierra-da.com.

Sierra Design Automation and Pinnacle are trademarks of Sierra Design Automation, Inc. All other trademarks are the property of their respective owners.