SINGLE-CRYSTAL CRITICAL DIMENSION REFERENCE MATERIALS DELIVERED BY NIST RESEARCHERS TO INTERNATIONAL SEMATECH.

NIST researchers have delivered prototype critical dimension reference materials for calibrating linewidth metrology instruments used in manufacturing semiconductor devices to International SEMATECH (ISMT) for evaluation by member companies. The work was the result of collaborations with ISMT, a private company, Sandia National Laboratories, and NIST to fabricate, test, and evaluate this new class of reference artifacts to meet the goals of the Semiconductor Industry Association's International Technology Roadmap for Semiconductors (ITRS). ITRS states that it is critically important to have suitable reference materials for lithography support available for development of advanced materials and process tools as well as on-wafer measurements for integrated circuit (IC) manufacturing. The ITRS projects the decrease of gate linewidths used in state-of-the-art IC manufacturing from present levels of approximately 250 nm to below 70 nm within several years. Until now, such reference materials have been unavailable because of the lack of a technology needed for their fabrication and certification.

In order to be compatible with users' metrology instruments, test chips containing the reference features were mounted in a "reference-material carrier" wafer also developed by NIST staff. This carrier consists of a blank 200 mm silicon wafer with a recessed "pocket" etched in the center with dimensions appropriate to accommodate the chip. Fifteen carrier wafers, each containing a chip with a reference feature having a critical dimension in a range from 80 nm to 140 nm, were delivered to ISMT for evaluation by its member companies.

The technical approach was to design the reference features into electrical test structures, thus enabling the determination of their electrical linewidth. A selection of 36 test structures was incorporated into the test chip that was patterned in the device layer of 110 silicon-on-insulator wafers based on well-established silicon micro-machining technology that produced feature side-walls having near-atomic planarity. Primary calibration of the critical dimension of the test-structures on all the test chips was accomplished by means of high cost, low speed High Resolution Transmission Electron Microscopy (HRTEM) imaging and lattice-plane counting at a limited number of sites on the wafer. HRTEM provides nanometer-level accuracy, but is sample-destructive and is prohibitively costly to implement on all reference features. The samples delivered to ISMT were calibrated via a statistical correlation with their high-precision electrical critical dimension measurement.