SDRAM Memory: DRAM And Beyond.

Between now and the year 2000, a broad spectrum of complex and high-speed memory architectures will enter the PC landscape. Currently, PC main memory is transitioning from EDO (Extended Data Out) memory to SDRAM (66MHz and 100MHz) with Synchronous DRAM expected to dominate the market during 1999 and the first half of 2000. At least four technologies are evolving from approximately 1998 to the year 2000: SDRAM, SDRAM II (DDR), SLDRAM (SyncLink), and Rambus. Table 1 is an approximate time-line regarding the emergence of future memory technologies.

Predicting where the "DRAM dust" will settle is difficult. All of the top ten DRAM manufacturers such as Samsung, Toshiba, and Hitachi are developing Rambus, yet also continuing aggressive R&D related to alternative next-generation DRAM technologies such as DDR. We thus find an intriguing blend of both partners and competitors working together. Nevertheless, and in spite of the unknowns, a general overview and explanation of where SDRAM and other future technologies may head will serve to give us a better grasp of key issues. In a market where change is the only constant, our goal is understanding rather than certainty.

To briefly cover subjects related to next generation memory, we will first explore factors driving the thirst for bandwidth within the PC industry. Second, definitions of each of the six memory technologies will assist us in comparing and contrasting the differences between these various technologies. And last, some thoughts on how Kingston fits into the overall industry evolution between now, the year 2000, and beyond.

BANDWIDTH AND THE "PERFORMANCE GAP"

Rapid advancements in both hardware and software are now emerging to meet acute performance needs within the PC industry. In fact, a number of years ago, Gordon Moore, the president and cofounder of Intel, predicted that CPU performance would double every 18 months (known as "Moore's Law"). Moore was right. From 1980 until now, the standard operating frequency of Intel and other microprocessors has increased roughly 100 times (5MHz to 500MHz). However, over the same time period the standard operating frequency of "page mode" DRAM memory has increased by roughly five times. Even newer Fast Page Mode, EDO, and SDRAM have only increased performance by roughly 15 times. There is a clear "Performance Gap" between processors and memory.

In the past, as microprocessors benefited from architectural and manufacturing enhancements, important enhancements for DRAMs have usually occurred in manufacturing. The density (storage capacity) of DRAMs has increased from roughly 1Kbit (thousand bits) to 64 - 128+Mbits (million bits) per chip. This in turn has reduced the number of DRAMs needed for memory, yet the design improvements required to accelerate DRAM data transfer rates have not kept pace. In short, transfer rates have not kept pace with density increases.

As for advancing software demands, the entrance of memory-intensive multimedia applications for both business and consumers is increasing the thirst for bandwidth. With advances in microprocessor frequency, in addition to software and design changes that shift multimedia processing to memory subsystems, PC main memory requirements could soon exceed 1GB (billion bytes). Furthermore, as advanced operating systems such as OS/2 and Windows NT become more complex, memory requirements will also rise to meet performance and feature demands.

In an attempt to address this performance gap, technology manufacturers have utilized various innovations. SRAMs (Static RAMs) were used to develop caches, which were helpful for various information processing applications, yet fell short when it came to graphic-intensive, multimedia applications. In addition, attempts were also made to widen the system bus that is used to pass data between the processor and DRAMs. As these buses are widened, signal integrity and timing become critical aspects of data transmission. The margin for error thus decreased given the wider bus, yet this further increased the need for more advanced and exacting memory technology.

Consequently, the need arises for new memory technologies that can deliver the required band-width. In addition to SDRAM, four other evolutionary memory technologies occupy the bandwidth landscape: SDRAM, VCM, DDR, SLDRAM, RDRAM, Concurrent RDRAM, and Direct RDRAM. A brief overview and definition of next- generation memory will serve to assist in both the understanding and future application of these emerging technologies.

SIX PLAYERS IN THE NEXT-GENERATION LANDSCAPE

DEFINITIONS

SDRAM

Synchronous DRAM (SDRAM) is "in synch" or synchronized to the system clock that controls the CPU. The clock that controls the microprocessor also controls the SDRAM, thus eliminating wait states and reducing data retrieval times. This synchronization allows the memory controller to know on which clock cycle data requests will be available. Data is thus input to the rising edge of the clock instead of with every two clock cycles (like EDO) or every three clock cycles (like FPM). SDRAM also utilizes multiple memory banks that function simultaneously, in addition to a burst mode feature that addresses an entire block rather than just one piece of data. SDRAM is currently in production.

VCM SDRAM

Virtual-channel memory is a variation of SDRAM incorporating 16 channels of independent cache lines to filter out page misses. The scheme is said to slash DRAM latency during the initial access. According to NEC, VCM requires smaller I/O interfaces and sense amplifiers, cutting power consumption by 30 percent over conventional SDRAM running at the same frequency.

SDRAM II (DDR)

Synchronous DRAM II or DDR (Double Data Rate) is the next generation of the current SDRAM.DDR finds its foundations on the same design core of SDRAM, yet adds advances to enhance its speed capabilities. There are two basic differences to the standard SDRAM: First, DDR uses more advanced synchronization circuitry not present on SDRAMs. And second, DDR uses a Delay-Locked Loop (DLL) to provide a DataStrobe signal as data becomes valid on the SDRAM pins. The controller can thus use this DataStrobe signal, one for every 16 outputs to locate data more accurately and resynchronize incoming data from different dual in-line memory modules. DDR essentially doubles the memory speed from SDRAMs without increasing the clock frequency. As a result, DDR allows data to be read on both the rising and the falling edge of the clock, thus delivering twice the bandwidth of standard SDRAMs. In addition, DDR moves to a higher frequency by changing signaling from TTL/LVTTL to SSTL3.

SLDRAM (SYNCLINK)

SLDRAM is a "joint effort" DRAM consortium that may be another competitor with Rambus. Development is coordinated through a consortium of twelve DRAM manufacturers and system companies. SLDRAM is an enhanced line extension of SDRAM architecture that extends the current four-bank design to 16 banks. In addition, SLDRAM adds a new interface and control logic, allowing use of packet protocols for memory-cell addressing, achieving a pin count of around 50 to 60. SLDRAM transfers data, like RDRAM, on each clock edge.

RDRAM

Rambus is a system-wide, chip-to-chip interface design that allows data transfer through a simplified bus that operates in a high frequency range. Think of the RDRAM design as an integrated, system-level rather than a chip-level approach. The key elements of the Rambus design include three parts: (1)The Rambus-based DRAMs (RDRAMs), (2) Rambus ASIC cells (RAGs), and (3) Interconnecting circuitry called the "Rambus Channel". Rambus, first used in graphics workstations in 1995, uses a unique RSL (Rambus Signaling Logic) technology that allows 600MHz transfer rates with conventional system and board design methodologies. Rambus is available in two flavors: RDRAM and Concurrent RDRAM. RDRAM is currently in production with Concurrent RDRAM production. The third line extension, Direct RDRAM, first shipped in 1998.

Rambus uses low voltage signal swings with data transfer on both edges of a synchronizing clock pulse. In addition, the RDRAM uses an 8-bit interface as compared to EDO/SDRAMs' use of a 4, 8, or 16-bit interface. Data is transferred on both edges of a high speed clock with Rambus utilizing a narrow bus.

In late 1996, Rambus agreed to a development and license contract with Intel that will lead to Intel's PC chip sets, supporting Rambus memory starting in late 1999. Currently, the Nintendo 64 video game utilizes Rambus technology for 3D graphics and CD audio. Standard PCs from Gateway and Micron in addition to add-in PC cards from companies, like Creative Labs, use Rambus memory.

DIRECT RAMBUS

Direct Rambus technology is an extension of today's RDRAMs. Direct RDRAMs use the same signaling (RSL: Rambus Signaling Level), but have a wider interface (16 bits), higher frequency at 800MHz, and improved protocol ([greater than]90% efficient). A single Direct RDRAM will deliver 1.6GB/sec; two supply 3.2GB/sec. A Direct Rambus uses two 8-bit channels to get 1.6GB and 3 channels to obtain 2.4GB (Table 2).

ANSWER TO THE PERFORMANCE GAP

Only companies that make major investments now in new equipment, technology, and personnel will be able to effectively provide virtual warehousing of SDRAMs, DDR, SLDRAM, and RDRAM memory modules as they emerge between now and the year 2000. The older, Fast Page Mode and Extended Data Out (EDO) memory product technology is much less complex than upcoming memory technologies, as noted in the preceding analysis. The upcoming memory technologies support much higher speed applications where even minute timing incompatibilities can cause major system problems.

Stuart Atkins is the marketing analyst and product manager of Kingston Technology (Fountain Valley, CA).

                                Comparisons
                          DDR                         Concurrent Direct
               SDRAM     SDRAM     SLDRAM     RDRAM     RDRAM    RDRAM
    Peak                                                          1.6
 Bandwidth   125MB/sec 200MB/sec 400MB/sec  600MB/sec 600MB/sec  GB/sec
    MHz       125MHz    200MHz     400MHz    600MHz     600MHz   800MHz
  Standard                         SLDRAM
    Body       JDEC      JDEC    Consortium  Rambus     Rambus   Rambus
Availability   1997      1998       1999      1995       1997     1999
  Voltage      3.3V      3.3V       2.5V      3.3V       3.3V     2.5V
Source: Toshiba and Rambus