SANYO Selects Ultima's Delay Calculator For Its Deep Submicron Timing Flow; High Accuracy Cell and Interconnect Delay Calculation is Key for Silicon Success.
SANYO uses Millennium for full-chip timing verification during pre- and post-layout design stages, and, in particular, for post-layout timing verification, a critical step necessary for silicon success.
According to Isao Ogura, Manager of Physical Design and CAD at SANYO, "We selected Millennium as a replacement for our existing tool based on its overall quality. After extensive benchmark testing, we found it to be the best in almost every category -- accuracy, capacity, speed and feature set. It gives us the most accurate delay data for our deep submicron designs."
"Japan's electronics industry is at the forefront of using deep submicron processes. They need and deserve the best-in-the class tools to assure silicon success," noted Joe G. Xi, Vice-president of Products and Marketing at Ultima. "By working closely with companies like SANYO, we were able to validate our tool under very demanding performance requirements."
Xi added, "Advanced deep submicron design solutions such as delay analysis require an intimate knowledge of market requirements, and fast response time to customers' requests. Our Japan distributor, Design Solutions, has an extremely experienced sales and technical team. In addition to this local support, our R&D staff in the U.S. is directly involved in almost every technical issue. With this technical team, we are able to offer high quality and exceptionally fast turnaround support to our customers in Japan."
About Millennium and Delay Calculation:
Contrary to the common belief that interconnect delay dominates gate delay in deep submicron design, it is not the interconnect delay itself that is significant, but rather the intricate interplays between interconnect network and cell's driving capability that are changing the way of delay and timing analysis. The Millennium delay calculator is designed specifically with this paradigm shift in mind. Millennium uses a proprietary, S-parameter interconnect modeling technology to calculate delays for multi-million gate designs with an accuracy within 5% of SPICE. By using standard interfaces such as DSPF, Verilog, VHDL and SDF, it is a critical link in a timing verification and timing-driven design flow. Since its first release, it has won every benchmark on accuracy and performance against other delay and timing analysis tools in the market.
About SANYO Electric Co., Ltd.:
SANYO Electric Co., designs and manufactures a broad range of electronic products including video and audio equipment, home appliances, industrial and commercial equipment, information systems, air-conditioning equipment, and other consumer products. SANYO also makes a wide array of semiconductors for those applications, including CCDs, flash memory, RISC microprocessors, image processing and data compression as well as digital imaging chips. SANYO semiconductor business saw double-digit growth in production during the 1997 fiscal year.
About Ultima Interconnect Technology, Inc.:
Ultima Interconnect Technology was founded in 1995. The company's tools and technologies address the impending crisis in deep sub-micron design by providing integrated design and layout analysis. In November 1996, Ultima was awarded a contract to develop 3D net extraction as part of Sematech's Chip Hierarchical Design System (CHDS). The Company's products are Nautilus(TM), a 3D Full Chip RC Extraction Tool; PRedator(TM), a Parasitic RC Reduction Tool; and Millennium, a DSM Delay Calculator. Ultima Interconnect Technology, Inc., 1139 Karlstad Drive, Sunnyvale, CA 94089, USA 408/734-0600, Fax: 408/734-0607, email@example.com, www.ultimatech.com
Contacts for Reader Inquiries:
Ultima Interconnect Technology, Inc., 1139 Karlstad Drive, Sunnyvale, CA 94089, USA 408/734-0600, Fax: 408/734-0607, firstname.lastname@example.org, www.ultimatech.com, Attn.: Joe G. Xi, email@example.com
Design Solutions, Inc, 2-15-10 Sin-Yokohama, Kouhoku-ku, Yokohama City, Kanagawa, Japan Tel: 045-474-8970, Fax: 045-474-8971, firstname.lastname@example.org, Attn: Tsuneo Suzuki
Acronyms and definitions: CAD: Computer-Aided Design CCD: Charge-Coupled Devices EDA: Electronic Design Automation DSPF: Detailed Standard Parasitic Format ECO: Engineering Change Order HDL: Hardware Description Language RC: Resistor Capacitor SDF: Standard Delay Format SPICE: popular circuit simulator
Note to Editors: Millennium, Nautilus, and PRedator are trademarks of Ultima Interconnect Technology, Inc. All other trademarks are the property of their respective owners.
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|Date:||Jan 4, 1999|
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