Routing high bit-rate connectors: the physical characteristics and routing tradeoffs of using 3.125 Gb/s parts. (Interconnect Strategies).

HIGH BIT-RATE I/O connectors play an important role in system-level differential signaling to and beyond 3.125 Gb/s. The physical characteristics of these connectors directly influence backplane and plug-in card PCB routing solutions. Understanding how different types of high bit-rate connectors affect board routing can simplify connector selection, signal assignment and routing.

High bit-rate connectors primarily use press-fit, through-hole pins. The size of the pin and its corresponding plated through-hole dimensions constrain minimum and maximum finished PCB thickness and the maximum number of signal layers. In complex backplanes, the aspect ratio of the drilled hole to the finished board thickness can exceed current plating thickness limits (around 8 mm, or 0.315"). Thick PCB substrates, and their longer plated through-hole feature dimensions, can lead to undesired stubs in interconnect routing topologies.

Characterized by dedicated reference pins for impedance control, high bit-rate connectors come in straight and right-angle forms with rectangular and staggered pin fields that can support from two to six differential signal pairs per row of pins. For optimal electrical performance, high bit-rate PCB circuits require relatively wide conductors. The pitch of the connector pin columns minus the nominal pad diameter determines the maximum routing channel width through which an edge-coupled, balanced differential pair can pass. The vertical pitch of pin rows minus the nominal pad diameter determines the potential for horizontal routing in the pin field.

The relative orientation of each differential signal pin pair is an important physical characteristic to consider. Differential signal pin pairs positioned at right angles to the connector body in right-angle connectors create a timing skew between the positive and negative signals as they pass through the connector. Signal pin reference plane voids must be scaled and sized according to the desired electrical specifications.

A primary challenge is the physical design of the pin field where the connector is attached to the PCB. This is true even when device signal pre-emphasis and equalization techniques are used to combat the frequency-dependent effects of system-level interconnects. Important tradeoffs to consider:

* Size of drill, finished hole and nominal pad, including tight tolerances for press-fit technology vs. Maximum finished board thickness

* Plane anti-pad shape and size required for targeted impedance control vs. Reference plane area beneath connector

* Maximum width of exit routing channels vs. Pin density and required routing area

* Number of signal layers required to fully route connector vs. Connector column depth, height and width

* Horizontal routing lanes in pin field vs. Horizontal and vertical routing lanes in connector area and routing difficulty pin field

* Parallel orientation of differential pin pairs in connector body pin field vs. Right-angle orientation of differential pin pairs in connector body routing difficulty level

* Use of lower justified signal routing layers to eliminate pin stubs vs. Counter boring to remove unwanted pin stubs

I have found it more difficult to accommodate differential signal polarity in PCB routing for edge-coupled lines on connectors whose signal pin pairs are oriented parallel (rather than at right angles) to the connector body. The desired differential signal polarity for a particular single layer routing solution is more easily achieved when signal pin pairs are oriented at right angles to the connector body (FIGURE 1).

[FIGURE 1 OMITTED]

Skew can be introduced by right-angle connectors in high bit-rate serial connections between plug-in cards. Compensate for skew by reversing the signal pin polarity assignments in the backplane routing (FIGURE 2). This approach to skew correction can be used in a surprising number of differential PCB routing situations involving local and system level interconnects.

[FIGURE 2 OMITTED]

REFERENCES

Gautam Patel and Kevin Ryan, "Designing 3.125 Gbps Backplane Systems," Electronica, November 2002.

Stilwell Baker Inc., internal research and correspondence.

Bill Wooddruff and Kevin Roselle, "Why 5G Is Critical for Intrasystem Link," Communications Design Conference, September 2002.

AMP-Tyco Electronics Corp. Z-PACK HM-Zd PWB Footprint Optimization for Routing, interconnect application note report #20GC015-1, rev. A, 2001.

BERNARD VOSS is the principal interconnect specialist at the consulting group Stilwell Baker Inc. (stilwellbaker.com).