Rich Library of Checkers Allows Easy Capture of Design Intent.

Business Editors/High-Tech Writers

SAN JOSE, Calif.--(BUSINESS WIRE)--March 13, 2000

0-In Design Automation, Inc. announced today that it has shipped the production release of 0-In Check, which includes the CheckerWare(TM) library, the industry's first white-box, reusable verification IP. White-box techniques take advantage of a design's internal structure to provide much more efficient and thorough functional verification.

Development Partners Guide CheckerWare Development

The CheckerWare library currently contains more than 45 different types of checkers for datapath elements, control structures, buses and interfaces in complex chip designs. Selection and design of the checkers were driven by analyses of difficult corner-case bugs in numerous multi-million-gate ASIC and system-on-chip (SOC) designs from 0-In's development partners. These chips include CPU, networking, telecommunications and IP designs, ensuring that the checkers are general enough to catch bugs in a wide variety of design styles.

0-In's CheckerWare development team in San Jose and Bangalore continuously augments the library with new checkers requested by customers. "Our development partners include some of the world's most advanced chip-design and verification engineers," said Dr. L. Curtis Widdoes, Jr., 0-In's CEO. "Tapping into their expertise has helped us to build a verification IP product that will provide value to design teams working on chip designs for diverse applications."

Reusable Verification IP Reduces Time-to-Market

Functional verification accounts for more than 60% of the time and effort in advanced ASIC design. Design teams reusing RTL code find that they cannot achieve their aggressive time-to-market goals without a verification methodology which allows them to also reuse their "verification IP". 0-In's innovative white-box techniques allow design and verification engineers to easily capture design intent and to instrument their designs by embedding 0-In directives in the RTL code.

Instrumentation by the design and verification engineers allows 0-In products to catch tough bugs that cannot be detected with low-level, automatically inferred, lint-type checkers. 0-In directives are embedded as comments so that the flow for other EDA tools is not perturbed. They become part of the design source and accompany the RTL code as it is reused in new applications. 0-In's powerful inference technology infers many details of checker hook-up directly from the RTL, so checkers automatically adapt to modifications made to the RTL code during reuse.

0-In Check Configures the Checkers

0-In Check is responsible for converting the directives into checkers for use in simulation. 0-In Check reads the RTL code, interprets the directives, configures the checkers for the current version of the RTL design and generates Verilog files implementing the checkers. These files are then included in any existing Verilog simulation block-level, chip-level or system-level. During simulation, the checkers monitor the RTL design during every cycle and report any violations of design intent. The 0-In View graphical user interface (GUI) utility helps to zero-in on the source of any violations.

Off-the-Shelf Complex Interface Monitors

Checkers may be combined to capture the protocol rules for complex buses and interfaces. 0-In offers off-the-shelf checker-based monitors for several popular standard interfaces, including PCI, SDRAM and UTOPIA. The CheckerWare library and all of the standard interface monitors are provided in Verilog source form, so they can be used as a starting point for design teams developing their own proprietary checkers.

Toughest Bugs are Between Blocks

Much of the effort in late-stage verification goes into finding obscure bugs between independently designed blocks. Improving block-level verification does not fully solve this problem. 0-In's products can be used to verify single blocks, groups of blocks, or even an entire chip, so they help find tough bugs between blocks. 0-In Check automatically configures the checkers for any type of simulation from block-level to chip-level.

0-In Checkers Enable 0-In Search

The same checkers embedded in the RTL design that detect bugs in simulation provide even more value when used with the 0-In Search product. 0-In Search employs advanced semi-formal verification technology to target the checkers.

0-In's semi-formal technology detects tough bugs that might otherwise be missed and greatly reduces the effort required to create thorough testbenches. 0-In Search starts with any existing testbench simulation including checkers, then "amplifies" the testbench, finding new ways to fire the checkers. 0-In Search works with groups of interconnected blocks within a design, as well as with individual blocks.

"One of the biggest issues we hear from our customers is that they do not want to adopt new languages in order to have access to the power of formal verification," said Dr. Widdoes. "0-In's tools allow the same checkers that run in simulation to be used by 0-In Search; there's no need for a new property language or constraint language. Furthermore, 0-In checkers are written in the same Verilog as the user's design, so customized checkers can be created without any new language at all."

The current production release of CheckerWare, 0-In Check, and the 0-In View utility is the first to the general market. Production release of 0-In Search is anticipated in the second quarter of 2000.

0-In Design Automation (pronounced "zero-in") is a privately held electronic design automation (EDA) company that develops tools that zero-in on functional bugs in ASIC and IC designs. 0-In was founded in 1996 and is based in San Jose, with a sales office in Boxborough, MA and distribution in Japan through Pacific Design Inc.

0-In Corporate Fact Sheet

Background

0-In Design Automation (pronounced "zero-in") helps ASIC and IC design teams zero-in on functional bugs -- so, development teams find bugs fast, and they find tough bugs before silicon.

While design size continues to grow exponentially, verification requirements grow even faster. Leading-edge teams now spend more than 60% of their time, effort, and resources functionally verifying their designs. Ensuring that a design meets specification is difficult enough; trying to find every bug is an enormous challenge.

0-In helps design teams accelerate the rate at which they find bugs. The company's white-box verification tools use a design's internal structure to provide more efficient, thorough verification. 0-In's two initial products, 0-In Check and 0-In Search, attack the two primary obstacles to finding bugs fast -- inadequate observability and inadequate controllability.

0-In's tools fit right into existing HDL-based methodologies -- requiring no design, testbench, or simulation changes. The tools help design teams harden individual blocks and rapidly verify them in-context, making 0-In's methodology ideal for system-on-chip (SOC) design and design reuse.

Products

0-In Check helps teams verify designs more efficiently by increasing observability during simulation. Designers can instrument their block interfaces with 0-In checkers to defend against illegal stimulus. Within blocks, they can instrument datapaths and control logic to ensure that they always function correctly, especially while handling corner cases.

CheckerWare is the industry's first white-box, reusable verification IP. CheckerWare is an extensive library of pre-verified checks that allows engineers to capture and verify design intent. 0-In Check adds these checkers to existing simulations to monitor design intent and report any violations. These same checkers are used as targets for 0-In Search.

0-In Search amplifies testbenches to find bugs that were never stimulated. It combines synthesis, simulation, and formal techniques to zero-in on bugs -- evaluating the equivalent of billions of new input combinations for every cycle of simulation. Designers amplify block-level tests with 0-In Search to find bugs they would otherwise miss. So, their HDL blocks are "hardened" prior to top-level integration. After integration, verification engineers use 0-In Search to amplify top-level simulations with respect to one or more blocks. Multiple-block capacity is important because the toughest bugs occur between individual blocks.

Management

Dr. L. Curtis Widdoes, Jr., Chairman & CEO

Dr. Widdoes is widely recognized as a pioneer in the computer-aided engineering industry. He has founded two successful EDA companies, Logic Modeling Systems Inc. (1987) and Valid Logic Systems Inc. (1981). Dr. Widdoes holds a B.S. in engineering and applied science from the California Institute of Technology and a Ph.D. in computer science from Stanford University. He holds four patents and is an IEEE W. Wallace McDowell Award recipient.

Steven D. White, Vice President of Operations

White was vice president of design verification at Synopsys, Inc. from 1994 to 1996. In that position he re-defined the company's verification strategy with thrusts into cycle-based simulation and emulation. Prior to Synopsys, White co-founded Logic Modeling Systems with Widdoes. White holds a B.A. from Michigan State University.

Dr. Mitchell J. Mlinar, Vice President of Engineering

Dr. Mlinar joined 0-In from Hewlett-Packard's EEsof division where he directed the engineering development of leading-edge RF and DSP synthesis products. During his career in EDA management, he has also been responsible for business growth and leadership in wireless communications and DSP products. Mlinar holds a B.S. in electrical engineering and computer science and an M.S. in solid-state physics from Marquette University, a Ph.D. in electrical and computer engineering from the University of Southern California, and two patents.

Thomas L. Anderson, Vice President of Applications Engineering

Anderson was formerly vice president of engineering at Virtual Chips, Inc., later the semiconductor IP group of Phoenix Technologies Ltd. He previously held design and EDA management positions at a number of semiconductor and system suppliers. Anderson holds a M.S. in electrical engineering and computer science from M.I.T. and a B.S. in computer systems engineering from the University of Massachusetts.

Headquarters: 1784 Technology Drive San Jose, CA 95110 Phone: [phone] Fax: [phone] Email: [e-mail]

Eastern Region: 1740 Massachusetts Avenue Boxborough, MA 01719 Phone: [phone]

Note to Editors: 0-In(TM) and CheckerWare(TM) are trademarks of 0-In Design Automation, Inc.