Browse Riazi, Abe

1-20 out of 20 article(s)

Title	Date	Words
Signal quality assessment: techniques for recognizing and minimizing signal integrity degradation.	Jun 1, 2007	1212
Effects of plane splits on high-speed signals, Part 2: signal and power integrity degradation can occur in PCBs and IC packages due to high-speed traces traversing plane-splits.	Apr 1, 2007	1178
Effects of plane splits on high-speed signals, part 1: a high-speed signal crossing splits of a reference plane can experience undesirable electrical impact.	Feb 1, 2007	1142
PBGA package lead modeling using TDR and IConnect: accurate modeling of package inner structures aids high-speed system-level simulations.	Dec 1, 2006	1385
Electrical interconnect modeling using R, L and C components: RLC modeling has fundamental importance.	Oct 1, 2006	1276
Timing analysis principles for digital PCBs, Part 3: on source synchronous designs: applications and timing characteristics.	Aug 1, 2006	1235
Timing analysis principles for digital PCBs, Part 2: a look at common-clock bus timing concepts.	Jun 1, 2006	1304
Timing analysis principles for digital PCBs, part I: timing concepts for digital design margin optimization and failure prevention.	Apr 1, 2006	976
Topology characteristics of reliable bus design: symmetry, minimized impedance discontinuities and balanced loading are preferred features.	Feb 1, 2006	1080
TDR for differential pair characterization, Part 2: single-ended and differential TDR signatures encompass broad signal integrity applications.	Dec 1, 2005	1242
TDR for differential pair characterization: not just another abbreviation, TDR is one more tool for analyzing single-ended and differential transmission lines.	Sep 1, 2005	1199
Loading effects on transmission lines, Part 2: a minimum loaded line impedance may be essential to your design.	Jun 1, 2005	1232
Loading effects on transmission lines, part 1: device loading can influence critical transmission line characteristics, and the design of high-speed PCBs.	May 1, 2005	1256
Length matching for high-speed differential pairs: loops and serpentines can add length to eliminate imbalance in your differential pairs.	Feb 1, 2005	821
Stub or no stub? Topology analysis can provide optimum system performance.	Oct 1, 2004	607
Avoiding differential pair: routing violations: take these steps to recognize and avoid layout mistakes when routing high-speed differential pairs.	Aug 1, 2004	1584
Differential signals routing requirements, Part II: for noise immunity, complementary transmitted signals need to be well balanced and trace impedances symmetrical.	Mar 1, 2004	457
Differential signals routing requirements: for noise immunity, complementary transmitted signals need to be well balanced and trace impedances symmetrical.	Feb 1, 2004	894
Via modeling for high-speed simulations, Part 2: a method for creating via models and integrating into a network topology for high-speed PCB simulations.	Oct 1, 2003	995
Via modeling for high-speed simulations, Part 1: a method for creating via models and integrating into a network topology for high-speed PCB simulations.	Sep 1, 2003	1034