Revision Of IEEE Verilog Standard Passes Major Milestone with Receipt of Nine Technology Donations.

Business Editors

PISCATAWAY, N.J.--(BUSINESS WIRE)--Sept. 4, 2003

The initiative to revise IEEE P1364(TM), "Standard for Verilog(R) Hardware Description Language," has passed a major milestone with the donation of nine substantial intellectual properties from four companies and the receipt of more than 50 additional enhancement suggestions for the standard.

The revision effort seeks to clarify ambiguities and unify the various extension proposals to create a single, next-generation Verilog(R) language. The overriding goal is to give chip designers and verification engineers better ways to develop integrated circuits by leveraging higher levels of abstraction. The donated properties will play a major role in accomplishing this objective.

Most of the packages donated to the Institute of Electrical and Electronics Engineers 1364 Working Group, also known as the Verilog Standards Group, have been proven in use. They provide concise but powerful constructs and utilities that can be consistently implemented by vendors and easily adopted by users. These packages, which were donated by Cadence Design Systems, Fintronic USA, Jeda Technologies and Verisity Ltd., are:

-- Design IP Encryption Extension,

-- Data Type Extension,

-- VPI Extensions,

-- Verification Extension,

-- Object Oriented Donation,

-- Separate Compilation Extension,

-- Systemtask-Based Randomization Library,

-- Transaction Record and Playback Extension, and

-- General Method for Future Extension of Verilog.

A description of each package appears in donor statements posted on the IEEE 1364 web site at http://www.verilog.com/IEEEVerilog.html.

The enhancement requests received provide added guidance in revising the standard. They cover a broad range of topics, such as the suggestion to incorporate the Accellera PSL Assertion language into the standard by reference and variable-width, floating-point modeling capability.

"It's heartening to have received so many complementary donations of technology," said Michael McNamara, Chair of the IEEE 1364 Working Group and Senior Vice President of Technology at Verisity. "The focus of the Working Group is to unify these extension proposals to create a modern standard addressing the complex needs of today's design teams, even as we remain true to the simple, concise roots of the original language.

"The revision is on track. We announced the approval of the project by the IEEE Standards Association Standards Board at the June 2003 Design Automation Conference in Anaheim along with a detailed roadmap for the entire project. We've begun partitioning these packages so various IEEE 1364 Task Forces can incorporate them into the appropriate sections of the language reference manual. The roadmap includes the open period for technology donations, which closed at the end of August. The final draft is due in December 2004. This will be followed by a six-month balloting cycle. We expect the standard to be available in mid 2005."

Anyone who creates Verilog-based products or uses the Verilog language in chip design and verification is invited to join the IEEE 1364 Working Group and help shape the next version of the Verilog standard. Those who wish to join can do so by visiting the IEEE 1364 web site.

For more information on the companies that donated technology packages, see:

-- Cadence Design Systems (NYSE:CDN, web http://www.cadence.com),

-- Fintronic USA, Inc. (http://www.fintronic.com )

-- Jeda Technologies, Inc. (http://www.jedatechnologies.com )

-- Verisity Ltd. (NASD:VRST, http://www.verisity.com ).

About Verilog and the IEEE 1364 Standard

Many tools in different domains, such as simulation, synthesis, analysis, power estimation, timing estimation, functional verification and formal verification, support the IEEE Verilog Hardware Description Language (HDL). These are developed and sold by more than a hundred companies. More than 200,000 licensed Verilog simulators are now in use.

Verilog was designed during the winter of 1983 at Gateway Design Automation. In 1990, Cadence Design Systems, which had purchased Gateway, formed Open Verilog International (OVI) to manage and promote the Verilog HDL as an international open standard.

In 1993, the IEEE approved OVI's request to develop an IEEE standard based on the Verilog HDL and accepted OVI's donation of the copyright to the language. The IEEE Verilog Standard Working Group began meeting in October of that year and submitted the completed standard to the IEEE in October 1995. The standard was approved in December and published in 1996.

Work on the first revision began in early 1997. This edition, IEEE 1364-2001, was published in September 2001.

About IEEE 1364 Working Group

To learn more about the IEEE 1364 Working Group, see, http://www.verilog.com. The group holds a teleconference at 8:30 a.m. Pacific time on the first Monday of each month. Work on the standard is done through task forces, each of which focuses on a specific aspect of the language. Participation in the IEEE 1364 Working Group is open to anyone who is interested in the standard.

About the IEEE Standards Association

The IEEE Standards Association, a globally recognized standards-setting body, develops consensus standards through an open process that brings diverse parts of an industry together. These standards set specifications and procedures based on current scientific consensus. The IEEE-SA has a portfolio of more than 870 completed standards and more than 400 standards in development. Over 15,000 IEEE members worldwide belong to IEEE-SA and voluntarily participate in standards activities. For further information on IEEE-SA see: http://www.standards.ieee.org.

About the IEEE

The IEEE has more than 380,000 members in approximately 150 countries. Through its members, the organization is a leading authority on areas ranging from aerospace, computers and telecommunications to biomedicine, electric power and consumer electronics. The IEEE produces nearly 30 percent of the world's literature in the electrical and electronics engineering, computing and control technology fields. This nonprofit organization also sponsors or cosponsors more than 300 technical conferences each year. Additional information about the IEEE can be found at http://www.ieee.org.

Verilog is a registered trademark of Cadence Designs Systems, Inc.