Renesas Technology to Introduce Single-chip SuperH Microcontrollers With USB2.0 Host, Audio and LCD Display Controller Functions for Car Digital Audio Products.SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif. -- Offering About 70 Percent Higher Speed Than Previous Renesas Solutions, the New MCUs Have the Performance Needed to Handle Control and Signal Processing See DSP. Tasks Renesas Technology Renesas Technology Corporation (ルネサス テクノロジ| America, Inc., a subsidiary of the world's largest supplier of microcontrollers, Renesas Technology Corp., today announced five SH7263 single-chip solutions for simplifying and reducing the cost of car audio, home audio, and similar digital audio systems that offer more performance and features. The new SuperH(R) 32-bit microcontrollers have a 200MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. , 32-bit SH-2A CPU CPU in full central processing unit Principal component of a digital computer, composed of a control unit, an instruction-decoding unit, and an arithmetic-logic unit. core with a built-in floating point unit (FPU (Floating Point Unit) A computer circuit that handles floating point operations. FPU - floating-point unit ) and include a USB USB in full Universal Serial Bus Type of serial bus that allows peripheral devices (disks, modems, printers, digitizers, data gloves, etc.) to be easily connected to a computer. 2.0 Host interface for portable-audio-player connectivity and an LCD controller for WVGA-size color screens. They also integrate a CD-ROM CD-ROM: see compact disc. CD-ROM in full compact disc read-only memory Type of computer storage medium that is read optically (e.g., by a laser). decoder and additional audio peripherals, among many other on-chip functions. Striving toward a goal that constantly incorporates advances "The ideal single-chip solution clearly is a moving target," said Paul Sykes
Paul Sykes (born 1943) is a British businessman, political donor, and friend and associate of the eurosceptic populist politician Robert Kilroy-Silk. , segment marketing manager, automotive business unit, Renesas Technology America, Inc. "System makers are constantly upgrading the performance and functionality of their products. Renesas, like other semiconductor manufacturers, constantly innovates, pushing technology limits to deliver chips that customers can use to produce designs with advanced features." Compared to the previous-generation 120MHz SH7261, the new 200MHz SH7263 microcontrollers deliver about 70 percent more speed, achieving 480 MIPS (Million Instructions Per Second) The execution speed of a computer. For example, .5 MIPS is 500,000 instructions per second; 100 MIPS is a hundred million instructions per second. (million instructions per second Noun 1. million instructions per second - (computer science) a unit for measuring the execution speed of a computer's CPU (but not the whole system); "4 MIPS is 4,000,000 instructions per second" MIPS ) and 400 MFLOPS See megaFLOPS. 1. (unit) MFLOPS - megaflops. 2. (benchmark) MFLOPS - A benchmark which attemps to estimate a system's floating-point "MFLOPS" rating for specific FADD, FSUB, FMUL and FDIV instruction mixes. C Source. Results, ftp://ftp.nosc. (mega floating-point number Noun 1. floating-point number - a number represented in floating-point notation number - a concept of quantity involving zero and units; "every number has a unique position in the sequence" operations per second) performance. Moreover, the new devices have a higher level of integration which includes a host interface that supports the Universal Serial Bus See USB. (hardware, standard) Universal Serial Bus - (USB) An external peripheral interface standard for communication between a computer and external peripherals over an inexpensive cable using biserial transmission. (USB) standard v2.0 High-Speed specification, and a display controller that supports color liquid crystal panels up to WVGA WVGA Wide Video Graphics Array (various physical sizes, 16:9 shape; 1.78:1 aspect ratio) WVGA West Virginia Golf Association (Charleston, West Virginia) size (800 x 480 pixels). They are also capable of supporting various digital audio CODEC (1) A hardware circuit that converts analog voice into PCM or ADPCM digital code and vice versa. The term may refer to only the A/D and D/A conversion, or it may include the compression technique for further reducing the signal (definition #2 below). See sampling and codec. middleware formats, including MP3, WMA (Windows Media Audio) An audio compression method from Microsoft. Known originally as MSAudio, this proprietary format competes with the MP3 and AAC methods. WMA encodes rapidly and is known to be especially effective at low bit rates. , and AAC (Advanced Audio Coding) An audio compression technology that is part of the MPEG-2 and MPEG-4 standards. AAC, especially MPEG-4 AAC, provides greater compression and better sound quality than MP3, which also came out of the MPEG standard. . The high processing performance that the SH7263 microcontrollers deliver lets customers implement multi-CODEC compatibility by software alone, for greater design flexibility. The devices also allow support for the Digital Rights Management (DRM (1) (Digital Radio Mondiale) A digital audio broadcasting (DAB) system for AM radio in Europe. See HD Radio. (2) (Digital Rights M ) required for audio content protection processing through music distribution. These capabilities are a response to strong customer demand for reducing the number of component parts by incorporating digital audio processing functions in the microcontrollers previously used mainly just for system control. Achieving higher ROM code efficiency The instruction set of the SH2A-FPU in the SH7263 and SH7203 microcontrollers is upward compatible See forward compatible. with those of the SH-2A and SH-2 CPU cores, allowing customers to reuse programs developed for existing products. At the same time, ROM code efficiency has been improved by approximately 75 percent compared with the SH-2 core, an improvement that makes it possible to reduce program size by approximately 25 percent. The high signal processing performance and ROM code efficiency enable MP3, WMA, AAC, and similar voice and music data compression data compression Process of reducing the amount of data needed for storage or transmission of a given piece of information (text, graphics, video, sound, etc.), typically by use of encoding techniques. and expansion processing to be executed by an SH7263 chip at a lower frequency and by a smaller program. As a result, system control and digital audio processing previously performed by separate chips can all be handled by an SH7263, so fewer components are needed. This makes it possible to implement a low-power-consumption system at lower cost. The SH7263 also incorporates many other functions ideal for audio systems. They include a sampling rate converter (SRC (SouRCe) Contrast with DST, which is an abbreviation of "destination." ) that converts the audio data sampling frequency, a serial sound interface (SSI (1) See server-side include and single-system image. (2) (Small-Scale Integration) Less than 100 transistors on a chip. See MSI, LSI, VLSI and ULSI. 1. (electronics) SSI - small scale integration. 2. ) for input and output of digital audio data, a serial communication interface with 16-stage FIFO (First In First Out) A storage method that retrieves the item stored for the longest time. Contrast with LIFO. See traffic engineering methods. FIFO - first-in first-out (SCIF (Sensitive Compartmented Information Facility) A Department of Defense (DOD) term for a secure room or datacenter that foils electronic surveillance and suppresses data leakage. ), and an I2C bus interface. There is also an 8-channel 10-bit A/D converter, a 2-channel 8-bit D/A converter, 8-channel direct memory access control (DMAC DMAC Direct Memory Access Controller DMAC Data Management and Communications DMAC N,N-Dimethylacetamide DMAC Downtown Media Arts Center (Orlando, Florida) DMAC Direct Memory Access Control DMAC Direct Machining and Control ), control area network (CAN) controller, and NAND flash controller. A 5-channel multifunction timer unit (MTU (1) (Maximum Transmission Unit, Maximum Transfer Unit) The largest frame size that can be transmitted over the network. For example, an Ethernet MTU is 1,500 bytes. Messages longer than the MTU must be divided into smaller frames. 2) is suitable for motor control and can produce a 3-phase pulse width modulation See PWM. (PWM (Pulse Width Modulation) A modulation technique that generates variable-width pulses to represent the amplitude of an analog input signal. Like its fixed-width pulse density modulation (PDM) cousin, the output switching transistor is on more of the time for a ) wave output for controlling AC motors. The company also announced the SH7203 microcontroller, which lacks the on-chip audio oriented functions and is suitable for many general consumer and industrial applications. Facilitating faster, easier system development On-chip debugging functions enable real-time debugging to be carried out at the maximum operating frequency. For the development environment, the USB bus-powered E10A-USB requiring no external power supply can be used as an emulator. The comprehensive range of hardware and software development tools available from Renesas and third parties includes the High-performance Embedded Workshop integrated development environment See IDE. integrated development environment - interactive development environment . MP3, WMA, AAC, and other voice-compression-standard compatible middleware products are also available, as are a CD-ROM ISO (1) See ISO speed. (2) (International Organization for Standardization, Geneva, Switzerland, www.iso.ch) An organization that sets international standards, founded in 1946. The U.S. member body is ANSI. 9660 file system and a HDD (Hard Disk Drive) See hard disk and HDD caddy. HDD - hard disk drive FAT32 file system.
Price and Availability
------- -------------- ------------------- -------------- ------------
Maximum Operating
Frequency Sample
Product (Operating On-Chip Price/
Name Type Name Temperature Range) Controllers Availability
------- -------------- ------------------- -------------- ------------
SH7263 R5S72630P200FP 200MHz CD-ROM 17.80/
(-40 to 85 degrees decoder, SRC July 2006
-------------- C) -------------- ------------
R5S72631P200FP CD-ROM 18.70/
decoder, SRC, July 2006
SD memory-
card IF(a)
-------------- -------------- ------------
R5S72632P200FP CD-ROM 18.70/
decoder, SRC, July 2006
IEBus
controller
-------------- -------------- ------------
R5S72633P200FP CD-ROM 19.60/
decoder, SRC July 2006
SD memory-
card IF(a),
IEBus
controller
------- -------------- ------------------- -------------- ------------
SH7203 R5S72030W200FP 200MHz -- 16.90/
(-20 to 85 degrees July 2006
C)
------- -------------- ------------------- -------------- ------------
(a) An SD memory card license must be obtained in order to use the SD
memory card interface.
Reader contact Readers can find additional product and contact information on the Renesas Technology Web site at www.renesas.com. About Renesas Technology Corp. Renesas Technology Corp. is one of the world's leading semiconductor system solutions providers for mobile, automotive and PC/AV (Audio Visual) markets and the world's No. 1 supplier of microcontrollers. It is also a leading provider of LCD Driver ICs, Smart Card microcontrollers, RF-ICs, High Power Amplifiers, Mixed Signal ICs, System-on-Chip (SoC), System-in-Package (SiP) and more. Established in 2003 as a joint venture between Hitachi, Ltd. (TOKYO:6501)(NYSE NYSE See: New York Stock Exchange :HIT) and Mitsubishi Electric Corporation (TOKYO:6503), Renesas Technology achieved consolidated revenue of 906 billion JPY JPY In currencies, this is the abbreviation for the Japanese Yen. Notes: The currency market, also known as the Foreign Exchange market, is the largest financial market in the world, with a daily average volume of over US $1 trillion. in FY2005 (end of March 2006). Renesas Technology is based in Tokyo, Japan and has a global network of manufacturing, design and sales operations in around 20 countries with about 26,200 employees worldwide. For further information, please visit http://www.renesas.com Note to Editors: A specification summary is included in this release, and a photo and block diagram of the SH7263 and SH7203 microcontrollers are available.
Notes: SuperH is a trademark of Renesas Technology Corp. CAN
(Controller Area Network) is a network specification for use
in vehicles, proposed by Robert Bosch GmbH of Germany. The SD
Memory Card is a small memory card whose specification was
originally formulated by 3C (Matsushita Electrical Industrial
Co., Ltd., Toshiba Corporation, and SanDisk Corporation) and
has been progressively extended by the SDA (SD Card
Association). (Renesas Technology Corp. is a member of the
SDA. http://www.sdcard.org/) I2C bus (Inter IC Bus) is an
interface specification proposed by Royal Philips Electronics
of the Netherlands. Other product names, company names, or
brands mentioned are the property of their respective owners.
Specifications:
Renesas Technology SH7263 & 7203 200MHz SuperH(R) Microcontrollers
with on-chip USB2.0 Host and LCD Controller
---------------- -----------------------------------------------------
Item SH7263/SH7203 Specifications
---------------- -----------------------------------------------------
Product name SH7263 SH7203
---------------- ------------------------------------------- ---------
Type name R5S72630 R5S72631 R5S72632 R5S72633 R5S72030
P200FP P200FP P200FP P200FP W200FP
---------------- -------- --------- ----------- ------------ ---------
Power supply 3.3V/1.2V
voltage
---------------- -----------------------------------------------------
Maximum
operating 200MHz
frequency
---------------- -----------------------------------------------------
Maximum At 200MHz operation: 480 MIPS (Dhrystone 1.1), 400
processing MFLOPS
performance
---------------- -----------------------------------------------------
Operating -20 to 85
temperature -40 to 85 degrees C degrees
range C
---------------- ------------------------------------------- ---------
CPU core SH2A-FPU
---------------- -----------------------------------------------------
CPU instructions 112 (including FPU-related instructions)
---------------- -----------------------------------------------------
On-chip RAM 80Kbytes
---------------- -----------------------------------------------------
Cache memory 16Kbytes (8KB instruction cache + 8KB data cache; 4-
way set associative type)
---------------- -----------------------------------------------------
External memory Bus clock: Max. 66MHz
-----------------------------------------------------
SRAM and SDRAM, directly connectable by bus-state
controller
-----------------------------------------------------
Address space: 64 Mbytes x 8
-----------------------------------------------------
Data bus width: External 8/16/32 bits
---------------- -----------------------------------------------------
On-chip Multifunction 16-bit timer (MTU2) x 5 channels
peripheral -----------------------------------------------------
functions 16-bit timer (CMT) x 2 channels
-----------------------------------------------------
A/D converter (10-bit resolution) x 8 channels
-----------------------------------------------------
D/A converter (8-bit resolution) x 2 channels
-----------------------------------------------------
Selection of USB standard v2.0 High-Speed
specification compatible Host or Function interface
-----------------------------------------------------
Serial communication interface with 16-stage FIFO
(SCIF) x 4 channels (asynchronous and synchronous
communication capability)
-----------------------------------------------------
Synchronous serial interface (SSU) x 2 channels
-----------------------------------------------------
I2C bus interface x 4 channels
-----------------------------------------------------
Serial sound interface (SSI) x 4 channels
-----------------------------------------------------
CAN controller (32-message buffer) x 2 channels
-----------------------------------------------------
NAND flash interface
-----------------------------------------------------
LCD display controller (LCDC), resolution up to 800 x
480 pixels (WVGA size)
-----------------------------------------------------
Real-time clock (RTC)
-----------------------------------------------------
CD-ROM decoder --
------------------------------------------- ---------
Sampling rate converter (SRC) --
------------------------------------------- ---------
-- -- IEBus IEBus --
controller controller
-------- --------- ----------- ------------ ---------
-- SD memory -- SD memory --
card IF card IF
-------- --------- ----------- ------------ ---------
User break controller (UBC)
-----------------------------------------------------
On-chip debugging functions
-- Advanced user debugger-II (AUD-II)
-- User debug interface (H-UDI)
-----------------------------------------------------
Direct memory access controller (DMAC) x 8 channels
-----------------------------------------------------
Interrupt controller (INTC)
-----------------------------------------------------
Watchdog timer (WDT)
-----------------------------------------------------
Clock pulse generator (CPG): Built-in PLL, max. 16x
multiplication
---------------- -----------------------------------------------------
Power-down modes Sleep
-----------------------------------------------------
Software standby
-----------------------------------------------------
Deep standby
-----------------------------------------------------
Module standby
---------------- -----------------------------------------------------
Package 240-pin QFP (32 mm x 32 mm)
---------------- -----------------------------------------------------
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