Renesas Technology Introduces Powerful RISC Microprocessor with Integrated Network Connectivity for Multitasking Embedded Systems Such as VoIP End Points.SAN JOSE San Jose, city, United States San Jose (sănəzā`, săn hōzā`), city (1990 pop. 782,248), seat of Santa Clara co., W central Calif.; founded 1777, inc. 1850. , Calif. -- Renesas Technology Renesas Technology Corporation (ルネサス テクノロジ| America, Inc. today announced the SH7619 SuperH(R)(1) 32-bit RISC RISC in full Reduced Instruction Set Computing Computer architecture that uses a limited number of instructions. RISC became popular in microprocessors in the 1980s. microprocessor, the company's first device to incorporate an IEEE-802.3 compliant Ethernet media access controller (MAC) and a physical layer (PHY See physical layer and physical. ) transceiver. This device can be used to enable network connectivity for a variety of products, including digital audio-visual equipment, office automation products, and factory automation systems. It is also ideal for consumer broadband voice-over-IP (VoIP) end points. Based on the 32-bit SH-2 RISC CPU CPU in full central processing unit Principal component of a digital computer, composed of a control unit, an instruction-decoding unit, and an arithmetic-logic unit. core, the SH7619 runs at a maximum frequency of 125 MHz (MegaHertZ) One million cycles per second. It is used to measure the transmission speed of electronic devices, including channels, buses and the computer's internal clock. A one-megahertz clock (1 MHz) means some number of bits (16, 32, 64, etc. and delivers 163 million instructions per second Noun 1. million instructions per second - (computer science) a unit for measuring the execution speed of a computer's CPU (but not the whole system); "4 MIPS is 4,000,000 instructions per second" MIPS (MIPS (Million Instructions Per Second) The execution speed of a computer. For example, .5 MIPS is 500,000 instructions per second; 100 MIPS is a hundred million instructions per second. ) of processing performance. The on-chip 16-KB 4-way set-associative cache helps improve the cache hit-rate in program execution. An additional 16-KB user RAM is available to store instructions and data for faster access. The SH7619 can execute TCP/IP TCP/IP in full Transmission Control Protocol/Internet Protocol Standard Internet communications protocols that allow digital computers to communicate over long distances. , middleware stacks, and other networking protocols at high speeds, and it enables the implementation of high-performance systems. The on-chip Ethernet MAC and PHY transceiver help reduce the component count and simplify the development of 10/100 Mbit/s Ethernet systems. Two dedicated direct memory access controller (DMAC DMAC Direct Memory Access Controller DMAC Data Management and Communications DMAC N,N-Dimethylacetamide DMAC Downtown Media Arts Center (Orlando, Florida) DMAC Direct Memory Access Control DMAC Direct Machining and Control ) channels with transmit and receive First In First Outs (FIFOs) of 512 bytes each facilitate high-speed data transfers over an Ethernet network. The SH7619's host interface function (HIF HIF Hypoxia Inducible Factor HIF Heavy Ion Fusion HIF Housing Inspection Foundation HIF Hammarby Idrottsförening (Swedish sport team) HIF Hey, It's Free (website) ) has an SRAM-equivalent interface that allows easy connection to the main microprocessor that performs system control functions in multi-processor systems. The HIF comprises a 16-bit interface bus and two SRAM See static RAM. SRAM - static random-access memory banks, each with a 1-KB linear address space. This function allows the main microprocessor to directly read from and write to the SRAM banks, and enables high-speed data transfers between the Ethernet port A socket on a computer or network device for plugging in an Ethernet cable. See WAN port. and the main microprocessor. Also, the HIF has a boot mode that allows a program stored in the flash memory connected to the main microprocessor to be downloaded via the host interface to the SDRAM (Synchronous DRAM) A type of dynamic RAM (DRAM) memory chip that has been widely used since the late 1990s. SDRAM chips eliminated wait states by dividing the chip into two cell blocks and interleaving data between them. connected to the SH7619 processor. This mode effectively eliminates the need for separate program storage for the SH7619. With the HIF, the development of a system's basic functions can be carried out in parallel with development of its network-connection related functions. The parallel development activities reduce the overall system design and debug To correct a problem in hardware or software. Debugging software means locating the errors in the source code (the program logic). Debugging hardware means finding errors in the circuit design (logical circuits) or in the physical interconnections of the circuits. time and simplify the process of adding an Ethernet connection function to an existing system. The SH7619 microprocessor includes a comprehensive set of on-chip peripherals. A general-purpose DMA (1) (Digital Media Adapter) See digital media hub. (2) (Document Management Alliance) A specification that provides a common interface for accessing and searching document databases. controller provides high-speed data transfers to and from external memory. An on-chip serial I/O interface See port and expansion slot. allows connection to a voice CODEC, facilitating the implementation of VoIP systems. To accelerate VoIP designs, Renesas is developing a low-cost consumer broadband VoIP analog telephone adapter A device that connects regular telephones to a broadband cable or DSL network for voice over IP (VoIP) service. The analog telephone adapter (ATA) provides the conversion between analog voice signals and IP packets, delivers dial tone and manages the call setup. (ATA (1) (AT Attachment) The specification for IDE drives. See IDE. (2) See analog telephone adapter. ATA - Advanced Technology Attachment ) reference design based on the SH7619. The design will include a complete package of VoIP middleware. The small (13 mm x 13 mm) 176-pin BGA (Ball Grid Array) A popular surface mount chip package that uses a grid of solder balls as its connectors. Available in plastic and ceramic varieties, BGA is noted for its compact size, high lead count and low inductance, which allows lower voltages to be used. package of the SH7619 helps minimize circuit board size. The device provides on-chip debugging functions that enable real-time debugging at the 125-MHz maximum operating frequency. For system debugging, the small PC-card-size E10A-USB can be used as an emulator.
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Sample Price/
Product Name Package Availability
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SH7619 (R4S76190) 176-pin BGA (13 mm x 13 mm) $15.00/Now
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Reader Contact Readers can find additional product and contact information on the Renesas Technology Web site at www.renesas.com. About Renesas Technology Corp. Renesas Technology Corp. designs and manufactures highly integrated semiconductor system solutions for mobile, automotive and PC/AV markets. Established on April 1, 2003 as a joint venture between Hitachi, Ltd. (TOKYO:6501)(NYSE NYSE See: New York Stock Exchange :HIT) and Mitsubishi Electric Corporation (TOKYO:6503) and headquartered in Tokyo, Japan, Renesas Technology is one of the largest semiconductor companies in the world and world leading microcontroller supplier globally. Besides microcontrollers, Renesas Technology offers system-on-chip devices, Smart Card ICs, mixed-signal products, flash memories, SRAMs and more. www.renesas.com Notes: (1) SuperH is a trademark of Renesas Technology Corp. Other product names, company names, or brands mentioned are the property of their respective owners.
Specifications: Renesas Technology SH7619 Processor with MAC and PHY
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Item SH7619
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Product name R4S76190
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Power supply voltage 1.8 V (internal)/3.3 V (external)
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Maximum operating 125 MHz
frequency
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Maximum processing 163 MIPS (at 125 MHz operation)
performance
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CPU core SH-2 (32-bit RISC)
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On-chip RAM 16 Kbytes
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Cache memory 16 Kbytes (mixed instructions/data, 4-way set-
associative type)
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Memory controller SRAM, SDRAM, ROM directly connectable;
PCMCIA interface incorporated
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Address space: 64 Mbytes x 5
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Provision for idle cycle insertion to prevent
bus collisions
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Data bus width: External 8/16/32 bits
(Upper 16 bits multiplexed with host interface)
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On-chip peripheral Ethernet controller x 1 channel
functions
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Ethernet physical layer transceiver (PHY) x 1
channel
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Dedicated Ethernet controller (MAC) x 2 channels
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General-purpose DMA controller x 4 channels
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Host interface function (1 Kbyte x 2 banks)
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Serial communication interface with FIFO (SCIF)
x 3 channels
(asynchronous and synchronous serial
communication capability)
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Serial IO with FIFO (SIOF) x 1 channel
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16-bit compare-match timer (CMT) x 2 channels
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On-chip debugging functions
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Interrupt controller (INTC)
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Watchdog timer (WDT)
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Clock pulse generator (CPG) with built-in
multiplication PLL
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I/O ports: 78
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Power-down modes Sleep mode
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Software Standby mode
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Module Standby mode
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Package 176-pin BGA (13 mm x 13 mm)
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